Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip
In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-a...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-12-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/23/23/9612 |
| _version_ | 1797399524677779456 |
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| author | Malik Summair Asghar Saad Arslan HyungWon Kim |
| author_facet | Malik Summair Asghar Saad Arslan HyungWon Kim |
| author_sort | Malik Summair Asghar |
| collection | DOAJ |
| description | In this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm<sup>2</sup> and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts. |
| first_indexed | 2024-03-09T01:42:31Z |
| format | Article |
| id | doaj.art-de1bb8bf982b45dca11dc53ad82b9e0d |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-09T01:42:31Z |
| publishDate | 2023-12-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-de1bb8bf982b45dca11dc53ad82b9e0d2023-12-08T15:26:35ZengMDPI AGSensors1424-82202023-12-012323961210.3390/s23239612Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing ChipMalik Summair Asghar0Saad Arslan1HyungWon Kim2Department of Electronics, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju 28644, Republic of KoreaTSY Design (Pvt.) Ltd., Islamabad 44000, PakistanDepartment of Electronics, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju 28644, Republic of KoreaIn this paper, we propose a compact and low-power mixed-signal approach to implementing convolutional operators that are often responsible for most of the chip area and power consumption of Convolutional Neural Network (CNN) processing chips. The convolutional operators consist of several multiply-and-accumulate (MAC) units. MAC units are the primary components that process convolutional layers and fully connected layers of CNN models. Analog implementation of MAC units opens a new paradigm for realizing low-power CNN processing chips, benefiting from less power and area consumption. The proposed mixed-signal convolutional operator comprises low-power binary-weighted current steering digital-to-analog conversion (DAC) circuits and accumulation capacitors. Compared with a conventional binary-weighted DAC, the proposed circuit benefits from optimum accuracy, smaller area, and lower power consumption due to its symmetric design. The proposed convolutional operator takes as input a set of 9-bit digital input feature data and weight parameters of the convolutional filter. It then calculates the convolutional filter’s result and accumulates the resulting voltage on capacitors. In addition, the convolutional operator employs a novel charge-sharing technique to process negative MAC results. We propose an analog max-pooling circuit that instantly selects the maximum input voltage. To demonstrate the performance of the proposed mixed-signal convolutional operator, we implemented a CNN processing chip consisting of 3 analog convolutional operators, with each operator processing a 3 × 3 kernel. This chip contains 27 MAC circuits, an analog max-pooling, and an analog-to-digital conversion (ADC) circuit. The mixed-signal CNN processing chip is implemented using a CMOS 55 nm process, which occupies a silicon area of 0.0559 mm<sup>2</sup> and consumes an average power of 540.6 μW. The proposed mixed-signal CNN processing chip offers an area reduction of 84.21% and an energy reduction of 91.85% compared with a conventional digital CNN processing chip. Moreover, another CNN processing chip is implemented with more analog convolutional operators to demonstrate the operation and structure of an example convolutional layer of a CNN model. Therefore, the proposed analog convolutional operator can be adapted in various CNN models as an alternative to digital counterparts.https://www.mdpi.com/1424-8220/23/23/9612mixed-signal convolutional operationanalog multiplierneural network acceleratorconvolutional neural networkartificial intelligenceneuromorphic engineering |
| spellingShingle | Malik Summair Asghar Saad Arslan HyungWon Kim Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip Sensors mixed-signal convolutional operation analog multiplier neural network accelerator convolutional neural network artificial intelligence neuromorphic engineering |
| title | Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip |
| title_full | Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip |
| title_fullStr | Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip |
| title_full_unstemmed | Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip |
| title_short | Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip |
| title_sort | analog convolutional operator circuit for low power mixed signal cnn processing chip |
| topic | mixed-signal convolutional operation analog multiplier neural network accelerator convolutional neural network artificial intelligence neuromorphic engineering |
| url | https://www.mdpi.com/1424-8220/23/23/9612 |
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