Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix
This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9165788/ |
| _version_ | 1819121037572308992 |
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| author | Vijender Kumar Sharma Jai Narayan Tripathi Hitesh Shrimali |
| author_facet | Vijender Kumar Sharma Jai Narayan Tripathi Hitesh Shrimali |
| author_sort | Vijender Kumar Sharma |
| collection | DOAJ |
| description | This article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc. |
| first_indexed | 2024-12-22T06:30:11Z |
| format | Article |
| id | doaj.art-de5d4cf4c92240a69038db8ee0779ec5 |
| institution | Directory Open Access Journal |
| issn | 2644-1225 |
| language | English |
| last_indexed | 2024-12-22T06:30:11Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj.art-de5d4cf4c92240a69038db8ee0779ec52022-12-21T18:35:44ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252020-01-01112413910.1109/OJCAS.2020.30160179165788Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance MatrixVijender Kumar Sharma0Jai Narayan Tripathi1https://orcid.org/0000-0001-9109-2948Hitesh Shrimali2https://orcid.org/0000-0003-2776-1005School of Computing and Electrical Engineering, Indian Institute of Technology Mandi, Mandi, IndiaDepartment of Electrical Engineering, Indian Institute of Technology Jodhpur, Jodhpur, IndiaSchool of Computing and Electrical Engineering, Indian Institute of Technology Mandi, Mandi, IndiaThis article presents two methods, the block approach indefinite admittance matrix (BA-IAM) and the estimation-by-inspection, to analyse the effects of deterministic noise on single-stage, single-ended amplifiers by extending the indefinite admittance matrix. The proposed methods are used to develop a generalised two-port network analysis for the commonly used amplifier topologies, in the presence of the supply, ground, bulk, and input noise sources. Various illustrative case studies (common-source, common-gate, and push-pull amplifiers) are considered to validate the analytical method of different CMOS technology nodes (180 nm, 110 nm, and 28 nm) and foundries (Lfoundry, UMC, and TSMC). Both the proposed methods are compared with the relevant existing methods in terms of mean percentage error (MPE), and computational complexity. The mathematically derived expressions using two methods show less than 4% MPE when compared with the schematic simulation results, obtained by the SPICE based simulations. Also, the post-layout simulations (PLS) results for all the examples (designed in CMOS 180 nm Lfoundry technology) show excellent matching with schematic simulations. The proposed methods can be further applicable to antennas, complex circuits, digital circuits, etc.https://ieeexplore.ieee.org/document/9165788/Two-port networkindefinite admittance matrix (IAM)amplifierdeterministic supply noise |
| spellingShingle | Vijender Kumar Sharma Jai Narayan Tripathi Hitesh Shrimali Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix IEEE Open Journal of Circuits and Systems Two-port network indefinite admittance matrix (IAM) amplifier deterministic supply noise |
| title | Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix |
| title_full | Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix |
| title_fullStr | Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix |
| title_full_unstemmed | Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix |
| title_short | Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix |
| title_sort | deterministic noise analysis for single stage amplifiers by extension of indefinite admittance matrix |
| topic | Two-port network indefinite admittance matrix (IAM) amplifier deterministic supply noise |
| url | https://ieeexplore.ieee.org/document/9165788/ |
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