Fully Parallel Proposal of Naive Bayes on FPGA

Fully Parallel Proposal of Naive Bayes on FPGA

This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gat...

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Bibliographic Details
Main Authors: Wysterlânya K. P. Barros, Matheus T. Barbosa, Leonardo A. Dias, Marcelo A. C. Fernandes
Format: Article
Language:English
Published: MDPI AG 2022-08-01
Series:Electronics
Subjects:
FPGA
hardware
machine learning
Naive Bayes
parallel implementation
Online Access:https://www.mdpi.com/2079-9292/11/16/2565

Internet

https://www.mdpi.com/2079-9292/11/16/2565

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