High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems
Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential i...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-05-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/12/5/560 |
| _version_ | 1797533982898782208 |
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| author | Zhun Zhang Xiang Wang Qiang Hao Dongdong Xu Jinlei Zhang Jiakang Liu Jinhui Ma |
| author_facet | Zhun Zhang Xiang Wang Qiang Hao Dongdong Xu Jinlei Zhang Jiakang Liu Jinhui Ma |
| author_sort | Zhun Zhang |
| collection | DOAJ |
| description | Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead. |
| first_indexed | 2024-03-10T11:23:24Z |
| format | Article |
| id | doaj.art-dea64682b9b546e6b7f2304d2db15464 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T11:23:24Z |
| publishDate | 2021-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-dea64682b9b546e6b7f2304d2db154642023-11-21T19:53:03ZengMDPI AGMicromachines2072-666X2021-05-0112556010.3390/mi12050560High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded SystemsZhun Zhang0Xiang Wang1Qiang Hao2Dongdong Xu3Jinlei Zhang4Jiakang Liu5Jinhui Ma6School of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaSchool of Electronic and Information Engineering, Beihang University, Beijing 100191, ChinaDynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.https://www.mdpi.com/2072-666X/12/5/560cryptographic acceleratordynamic data securityAES-GCMhardware securitySoC |
| spellingShingle | Zhun Zhang Xiang Wang Qiang Hao Dongdong Xu Jinlei Zhang Jiakang Liu Jinhui Ma High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems Micromachines cryptographic accelerator dynamic data security AES-GCM hardware security SoC |
| title | High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems |
| title_full | High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems |
| title_fullStr | High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems |
| title_full_unstemmed | High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems |
| title_short | High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems |
| title_sort | high efficiency parallel cryptographic accelerator for real time guaranteeing dynamic data security in embedded systems |
| topic | cryptographic accelerator dynamic data security AES-GCM hardware security SoC |
| url | https://www.mdpi.com/2072-666X/12/5/560 |
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