Latency-Aware Accelerator of SIMECK Lightweight Block Cipher

Latency-Aware Accelerator of SIMECK Lightweight Block Cipher

This article presents a latency-optimized implementation of the SIMECK lightweight block cipher on a field-programmable-gate-array (FPGA) platform with a block and key lengths of 32 and 64 bits. The critical features of our architecture include parallelism, pipelining, and a dedicated controller. Pa...

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Bibliographic Details
Main Authors: Adel R. Alharbi, Hassan Tariq, Amer Aljaedi, Abdullah Aljuhni
Format: Article
Language:English
Published: MDPI AG 2022-12-01
Series:Applied Sciences
Subjects:
cryptography
lightweight
block cipher
SIMECK
RFID
WSNs
Online Access:https://www.mdpi.com/2076-3417/13/1/161

Internet

https://www.mdpi.com/2076-3417/13/1/161

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