A Multiplier-less Implementation of Two-Dimensional Circular-Support Wavelet Transform on FPGA
In this paper, a two-dimensional (2-D) circular-support wavelet transform (2-D CSWT) is presented. 2-D CSWT is a new geometrical image transform, which can efficiently represent images using 2-D circular spectral split schemes (circularlydecomposed frequency subspaces). 2-D all-pass functions and...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
College of Engineering, University of Basrah
2015-06-01
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| Series: | Iraqi Journal for Electrical and Electronic Engineering |
| Subjects: | |
| Online Access: | http://ijeee.org/volums/volume9/IJEEE9PDF/paper92.pdf |
| Summary: | In this paper, a two-dimensional (2-D) circular-support wavelet transform (2-D
CSWT) is presented. 2-D CSWT is a new geometrical image transform, which can
efficiently represent images using 2-D circular spectral split schemes (circularlydecomposed
frequency subspaces). 2-D all-pass functions and lattice structure are
used to produce 1-level circular symmetric 2-D discrete wavelet transform with
approximate linear phase 2-D filters. The classical one-dimensional (1-D) analysis
Haar filter bank branches H0(z) and H1(z) which work as low-pass and high-pass
filters, respectively are transformed into their 2-D counterparts H0(z1,z2) and H1(z1,z2)
by applying a circular-support version of the digital spectral transformation (DST).
The designed 2-D wavelet filter bank is realized in a separable architecture. The
proposed architecture is simulated using Matlab program to measure the deflection
ratio (DR) of the high frequency coefficient to evaluate its performance and compare
it with the performance of the classical 2-D wavelet architecture. The correlation
factor between the input and reconstructed images is also calculated for both
architectures. The FPGA (Spartan-3E) Kit is used to implement the resulting
architecture in a multiplier-less manner and to calculate the die area and the critical
path or maximum frequency of operation. The achieved multiplier-less
implementation takes a very small area from FPGA Kit (the die area in 3-level
wavelet decomposition takes 300 slices with 7% occupation ratio only at a maximum
frequency of 198.447 MHz). |
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| ISSN: | 1814-5892 2078-6069 |