Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference
A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors (<inline-formula&g...
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9923910/ |
| _version_ | 1797985724522299392 |
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| author | Ximing Fu Dalton Martini Colombo Yadong Yin Kamal El-Sankary |
| author_facet | Ximing Fu Dalton Martini Colombo Yadong Yin Kamal El-Sankary |
| author_sort | Ximing Fu |
| collection | DOAJ |
| description | A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors (<inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {GS}}$ </tex-math></inline-formula>) operating in weak inversion mode, while the second one (<inline-formula> <tex-math notation="LaTeX">$V_{\text {NL}}$ </tex-math></inline-formula>) is generated using a nonlinear current created by a piecewise-linear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a low-power pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard <inline-formula> <tex-math notation="LaTeX">$0.18 \mathrm {\mu m}$ </tex-math></inline-formula> CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5–15 ppm/°C in the temperature range of −10 °C to 110 °C, whereas the simulated results demonstrate a similar performance within the temperature range of −40 °C to 150 °C. The supply current consumption is <inline-formula> <tex-math notation="LaTeX">$150 ~\mu \text{A}$ </tex-math></inline-formula>, and the chip area is <inline-formula> <tex-math notation="LaTeX">$0.56\times0.8$ </tex-math></inline-formula> mm2. The measured peak noise at the output is <inline-formula> <tex-math notation="LaTeX">$1.42 ~\mu \text{V}/\sqrt {\text {Hz}} $ </tex-math></inline-formula> @320 Hz, the measured PSRR @ 1 kHz is −80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance. |
| first_indexed | 2024-04-11T07:21:30Z |
| format | Article |
| id | doaj.art-e09779c0b62e461887e31c2c8d64056b |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-11T07:21:30Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
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| spelling | doaj.art-e09779c0b62e461887e31c2c8d64056b2022-12-22T04:37:11ZengIEEEIEEE Access2169-35362022-01-011011097011098210.1109/ACCESS.2022.32155449923910Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap ReferenceXiming Fu0https://orcid.org/0000-0002-1788-2607Dalton Martini Colombo1https://orcid.org/0000-0002-6781-9673Yadong Yin2https://orcid.org/0000-0003-4900-8348Kamal El-Sankary3https://orcid.org/0000-0001-8104-6913Department of Electrical and Computer Engineering, Dalhousie University, Halifax, CanadaElectrical Engineering Department, Federal University of Minas Gerais, Belo Horizonte, BrazilSchool of Physics and Information Engineering, Fuzhou University, Fuzhou, ChinaDepartment of Electrical and Computer Engineering, Dalhousie University, Halifax, CanadaA Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors (<inline-formula> <tex-math notation="LaTeX">$\Delta V_{\mathrm {GS}}$ </tex-math></inline-formula>) operating in weak inversion mode, while the second one (<inline-formula> <tex-math notation="LaTeX">$V_{\text {NL}}$ </tex-math></inline-formula>) is generated using a nonlinear current created by a piecewise-linear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a low-power pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard <inline-formula> <tex-math notation="LaTeX">$0.18 \mathrm {\mu m}$ </tex-math></inline-formula> CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5–15 ppm/°C in the temperature range of −10 °C to 110 °C, whereas the simulated results demonstrate a similar performance within the temperature range of −40 °C to 150 °C. The supply current consumption is <inline-formula> <tex-math notation="LaTeX">$150 ~\mu \text{A}$ </tex-math></inline-formula>, and the chip area is <inline-formula> <tex-math notation="LaTeX">$0.56\times0.8$ </tex-math></inline-formula> mm2. The measured peak noise at the output is <inline-formula> <tex-math notation="LaTeX">$1.42 ~\mu \text{V}/\sqrt {\text {Hz}} $ </tex-math></inline-formula> @320 Hz, the measured PSRR @ 1 kHz is −80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance.https://ieeexplore.ieee.org/document/9923910/Pre-regulatorBGRcurvature compensationlow-power operationlow areasubthreshold |
| spellingShingle | Ximing Fu Dalton Martini Colombo Yadong Yin Kamal El-Sankary Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference IEEE Access Pre-regulator BGR curvature compensation low-power operation low area subthreshold |
| title | Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference |
| title_full | Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference |
| title_fullStr | Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference |
| title_full_unstemmed | Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference |
| title_short | Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference |
| title_sort | low noise high psrr high order piecewise curvature compensated cmos bandgap reference |
| topic | Pre-regulator BGR curvature compensation low-power operation low area subthreshold |
| url | https://ieeexplore.ieee.org/document/9923910/ |
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