Asynchronous SAR ADC with self‐timed track‐and‐hold
Abstract This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolong...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-11-01
|
| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.13026 |
| _version_ | 1797449176792956928 |
|---|---|
| author | Sunghyun Bae Sewon Lee Siheon Seong Jiwon Woo Minjae Lee |
| author_facet | Sunghyun Bae Sewon Lee Siheon Seong Jiwon Woo Minjae Lee |
| author_sort | Sunghyun Bae |
| collection | DOAJ |
| description | Abstract This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases. |
| first_indexed | 2024-03-09T14:21:51Z |
| format | Article |
| id | doaj.art-e15a30fddb98430db2473f1038c083eb |
| institution | Directory Open Access Journal |
| issn | 0013-5194 1350-911X |
| language | English |
| last_indexed | 2024-03-09T14:21:51Z |
| publishDate | 2023-11-01 |
| publisher | Wiley |
| record_format | Article |
| series | Electronics Letters |
| spelling | doaj.art-e15a30fddb98430db2473f1038c083eb2023-11-28T11:20:34ZengWileyElectronics Letters0013-51941350-911X2023-11-015922n/an/a10.1049/ell2.13026Asynchronous SAR ADC with self‐timed track‐and‐holdSunghyun Bae0Sewon Lee1Siheon Seong2Jiwon Woo3Minjae Lee4School of Electrical Engineering and Computer Science Gwangju Institute of Science and Technology Gwangju South KoreaSchool of Electrical Engineering and Computer Science Gwangju Institute of Science and Technology Gwangju South KoreaR&D Department Aconic Inc. Gwangju Republic of KoreaR&D Department Aconic Inc. Gwangju Republic of KoreaSchool of Electrical Engineering and Computer Science Gwangju Institute of Science and Technology Gwangju South KoreaAbstract This paper presents an asynchronous SAR ADC featuring a self‐timed track‐and‐hold (STH) architecture. The design aims to address the common timing issue of divider‐based clock generation, where the fixed‐time track‐and‐hold (FTH) period often results in incomplete conversions due to prolonged conversion times time due to comparator metastability. To alleviate the degradation of the ENOB induced by these delays, the proposed STH method is introduced so that more conversion period is secured without requiring a high‐speed input clock. Based on measurements, the proposed STH method achieves up to 0.7 bit improvement over the conventional FTH approach as conversion time increases.https://doi.org/10.1049/ell2.13026analogue‐digital conversionmixed analogue‐digital integrated circuits |
| spellingShingle | Sunghyun Bae Sewon Lee Siheon Seong Jiwon Woo Minjae Lee Asynchronous SAR ADC with self‐timed track‐and‐hold Electronics Letters analogue‐digital conversion mixed analogue‐digital integrated circuits |
| title | Asynchronous SAR ADC with self‐timed track‐and‐hold |
| title_full | Asynchronous SAR ADC with self‐timed track‐and‐hold |
| title_fullStr | Asynchronous SAR ADC with self‐timed track‐and‐hold |
| title_full_unstemmed | Asynchronous SAR ADC with self‐timed track‐and‐hold |
| title_short | Asynchronous SAR ADC with self‐timed track‐and‐hold |
| title_sort | asynchronous sar adc with self timed track and hold |
| topic | analogue‐digital conversion mixed analogue‐digital integrated circuits |
| url | https://doi.org/10.1049/ell2.13026 |
| work_keys_str_mv | AT sunghyunbae asynchronoussaradcwithselftimedtrackandhold AT sewonlee asynchronoussaradcwithselftimedtrackandhold AT siheonseong asynchronoussaradcwithselftimedtrackandhold AT jiwonwoo asynchronoussaradcwithselftimedtrackandhold AT minjaelee asynchronoussaradcwithselftimedtrackandhold |