NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory
In this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neur...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2022-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9899406/ |
| _version_ | 1797997369128648704 |
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| author | Jung Nam Kim Jaehong Lee Jo Eun Kim Suck Won Hong Minsuk Koo Yoon Kim |
| author_facet | Jung Nam Kim Jaehong Lee Jo Eun Kim Suck Won Hong Minsuk Koo Yoon Kim |
| author_sort | Jung Nam Kim |
| collection | DOAJ |
| description | In this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neural network on a limited-size hardware chip. We designed a full array architecture including a stacked layer selection circuit. In addition, we investigated the synaptic characteristics of CTF device by using technology computer-aided design (TCAD) simulation. We demonstrated the feasibility of the synapse array for neural network accelerators through a system-level MATLAB simulation with the Modified National Institute of Standards and Technology (MNIST) database. |
| first_indexed | 2024-04-11T10:31:51Z |
| format | Article |
| id | doaj.art-e2270dbe337f460780bbd5f2f8e2d567 |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-04-11T10:31:51Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-e2270dbe337f460780bbd5f2f8e2d5672022-12-22T04:29:25ZengIEEEIEEE Journal of the Electron Devices Society2168-67342022-01-011081382010.1109/JEDS.2022.32082419899406NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash MemoryJung Nam Kim0Jaehong Lee1Jo Eun Kim2Suck Won Hong3Minsuk Koo4https://orcid.org/0000-0003-2522-6754Yoon Kim5https://orcid.org/0000-0002-4837-8411School of Electrical and Computer Engineering, University of Seoul, Seoul, South KoreaSamsung Electronics Company Ltd., Hwaseong, South KoreSchool of Electrical and Computer Engineering, University of Seoul, Seoul, South KoreaDepartment of Optics and Mechatronics Engineering, Pusan National University, Busan, South KoreaDepartment of Computer Science and Engineering, Incheon National University, Incheon, South KoreaSchool of Electrical and Computer Engineering, University of Seoul, Seoul, South KoreaIn this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neural network on a limited-size hardware chip. We designed a full array architecture including a stacked layer selection circuit. In addition, we investigated the synaptic characteristics of CTF device by using technology computer-aided design (TCAD) simulation. We demonstrated the feasibility of the synapse array for neural network accelerators through a system-level MATLAB simulation with the Modified National Institute of Standards and Technology (MNIST) database.https://ieeexplore.ieee.org/document/9899406/3-D stacked synapse arrayneuromorphic systemartificial neural networksynapse arraysynapse deviceCTF memory |
| spellingShingle | Jung Nam Kim Jaehong Lee Jo Eun Kim Suck Won Hong Minsuk Koo Yoon Kim NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory IEEE Journal of the Electron Devices Society 3-D stacked synapse array neuromorphic system artificial neural network synapse array synapse device CTF memory |
| title | NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory |
| title_full | NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory |
| title_fullStr | NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory |
| title_full_unstemmed | NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory |
| title_short | NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory |
| title_sort | nor type 3 d synapse array architecture based on charge trap flash memory |
| topic | 3-D stacked synapse array neuromorphic system artificial neural network synapse array synapse device CTF memory |
| url | https://ieeexplore.ieee.org/document/9899406/ |
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