A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing

This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine...

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Main Authors: Reza Iravani, Houshang Karimi, Amir Etemadi, Mahmoud Matar
Format: Article
Language:English
Published: MDPI AG 2012-06-01
Series:Energies
Subjects:
Online Access:http://www.mdpi.com/1996-1073/5/6/1713
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author Reza Iravani
Houshang Karimi
Amir Etemadi
Mahmoud Matar
author_facet Reza Iravani
Houshang Karimi
Amir Etemadi
Mahmoud Matar
author_sort Reza Iravani
collection DOAJ
description This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The proposed hardware architecture is realized based on the FPGA technology. The simulator is tested and its CHIL capability verified based on the closed-loop testing of a robust multivariable servomechanism controller for autonomous operation of a distributed generation unit.
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spelling doaj.art-e235e2c97dd04f7295c52d066f656bae2022-12-22T03:08:48ZengMDPI AGEnergies1996-10732012-06-01561713173310.3390/en5061713A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop TestingReza IravaniHoushang KarimiAmir EtemadiMahmoud MatarThis paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The proposed hardware architecture is realized based on the FPGA technology. The simulator is tested and its CHIL capability verified based on the closed-loop testing of a robust multivariable servomechanism controller for autonomous operation of a distributed generation unit.http://www.mdpi.com/1996-1073/5/6/1713real-time simulationelectromagnetic transientsdistributed generationpower electronics interfacemodelingFPGA
spellingShingle Reza Iravani
Houshang Karimi
Amir Etemadi
Mahmoud Matar
A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing
Energies
real-time simulation
electromagnetic transients
distributed generation
power electronics interface
modeling
FPGA
title A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing
title_full A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing
title_fullStr A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing
title_full_unstemmed A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing
title_short A High Performance Real-Time Simulator for Controllers Hardware-in-the-Loop Testing
title_sort high performance real time simulator for controllers hardware in the loop testing
topic real-time simulation
electromagnetic transients
distributed generation
power electronics interface
modeling
FPGA
url http://www.mdpi.com/1996-1073/5/6/1713
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