Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits
We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above cr...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-02-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/14/3/581 |
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| author | G. Lakshmi Priya Puneet Saran Shikhar Kumar Padhy Prateek Agarwal A. Andrew Roobert L. Jerart Julus |
| author_facet | G. Lakshmi Priya Puneet Saran Shikhar Kumar Padhy Prateek Agarwal A. Andrew Roobert L. Jerart Julus |
| author_sort | G. Lakshmi Priya |
| collection | DOAJ |
| description | We live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications. |
| first_indexed | 2024-03-11T06:10:47Z |
| format | Article |
| id | doaj.art-e23a420c70cf41a082512228faaccc07 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-11T06:10:47Z |
| publishDate | 2023-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-e23a420c70cf41a082512228faaccc072023-11-17T12:42:48ZengMDPI AGMicromachines2072-666X2023-02-0114358110.3390/mi14030581Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM CircuitsG. Lakshmi Priya0Puneet Saran1Shikhar Kumar Padhy2Prateek Agarwal3A. Andrew Roobert4L. Jerart Julus5Centre for Innovation and Product Development, Vellore Institute of Technology, Chennai 600127, IndiaSchool of Electronics Engineering, Vellore Institute of Technology, Chennai 600127, IndiaSchool of Electronics Engineering, Vellore Institute of Technology, Chennai 600127, IndiaSchool of Electronics Engineering, Vellore Institute of Technology, Chennai 600127, IndiaDepartment of ECE, Francis Xavier Engineering College, Tirunelveli 627003, IndiaDepartment of IT, National Engineering College, Kovilpatti 628503, IndiaWe live in a technologically advanced society where we all use semiconductor chips in the majority of our gadgets, and the basic criterion concerning data storage and memory is a small footprint and low power consumption. SRAM is a very important part of this and can be used to meet all the above criteria. In this study, LTSpice software is used to come up with a high-performance sense amplifier circuit for low-power SRAM applications. Throughout this research, various power reduction approaches were explored, and the optimal solution has been implemented in our own modified SRAM design. In this article, the effect of power consumption and the reaction time of the suggested sense amplifier were also examined by adjusting the width-to-length (W/L) ratio of the transistor, the power supply, and the nanoscale technology. The exact amount of power used and the number of transistors required by different approaches to better comprehend the ideal technique are also provided. Our proposed design of a low-power sense amplifier has shown promising results, and we employ three variations of VLSI power reduction techniques to improve efficiency. Low-power SRAMs embrace the future of memory-centric neuromorphic computing applications.https://www.mdpi.com/2072-666X/14/3/581sense amplifierlow powerSRAMhigh speedModified Cross-Coupled |
| spellingShingle | G. Lakshmi Priya Puneet Saran Shikhar Kumar Padhy Prateek Agarwal A. Andrew Roobert L. Jerart Julus Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits Micromachines sense amplifier low power SRAM high speed Modified Cross-Coupled |
| title | Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits |
| title_full | Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits |
| title_fullStr | Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits |
| title_full_unstemmed | Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits |
| title_short | Novel Low Power Cross-Coupled FET-Based Sense Amplifier Design for High-Speed SRAM Circuits |
| title_sort | novel low power cross coupled fet based sense amplifier design for high speed sram circuits |
| topic | sense amplifier low power SRAM high speed Modified Cross-Coupled |
| url | https://www.mdpi.com/2072-666X/14/3/581 |
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