Rapid prototyping of Networks-on-Chip on multi-FPGA platforms
Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for a...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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EDP Sciences
2016-01-01
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| Series: | MATEC Web of Conferences |
| Online Access: | http://dx.doi.org/10.1051/matecconf/20165412002 |
| _version_ | 1818575832515346432 |
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| author | Tan Junyan Fresse Virginie Rousseau Frédéric |
| author_facet | Tan Junyan Fresse Virginie Rousseau Frédéric |
| author_sort | Tan Junyan |
| collection | DOAJ |
| description | Experimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of NoC solutions. The efficiency of our approach is illustrated through the deployment of the Hermes NoC and its exploration on several FPGA platforms. |
| first_indexed | 2024-12-15T00:46:17Z |
| format | Article |
| id | doaj.art-e2b0133210f84a938ddf7f9351bd5b49 |
| institution | Directory Open Access Journal |
| issn | 2261-236X |
| language | English |
| last_indexed | 2024-12-15T00:46:17Z |
| publishDate | 2016-01-01 |
| publisher | EDP Sciences |
| record_format | Article |
| series | MATEC Web of Conferences |
| spelling | doaj.art-e2b0133210f84a938ddf7f9351bd5b492022-12-21T22:41:32ZengEDP SciencesMATEC Web of Conferences2261-236X2016-01-01541200210.1051/matecconf/20165412002matecconf_mimt2016_12002Rapid prototyping of Networks-on-Chip on multi-FPGA platformsTan Junyan0Fresse Virginie1Rousseau Frédéric2College of IoT, Hohai UniversityHubert Curien Laboratory UMR CNRS 5516TIMA Laboratory, UJF/CNRS/Grenoble INPExperimental approaches used for architecture exploration and validation are often based on configurable logic device such as FPGA. NoC architectures require multi-FPGA platforms as the resources of a single FPGA are not big enough. Partitionning a NoC on multi-FPGA requires special techniques for allocating communication channels, physical links and suitable resource allocation scheme. We present a scalable emulation platform and its associated design flow based on a multi FPGA approach that allows quick exploration, evaluation and comparison of NoC solutions. The efficiency of our approach is illustrated through the deployment of the Hermes NoC and its exploration on several FPGA platforms.http://dx.doi.org/10.1051/matecconf/20165412002 |
| spellingShingle | Tan Junyan Fresse Virginie Rousseau Frédéric Rapid prototyping of Networks-on-Chip on multi-FPGA platforms MATEC Web of Conferences |
| title | Rapid prototyping of Networks-on-Chip on multi-FPGA platforms |
| title_full | Rapid prototyping of Networks-on-Chip on multi-FPGA platforms |
| title_fullStr | Rapid prototyping of Networks-on-Chip on multi-FPGA platforms |
| title_full_unstemmed | Rapid prototyping of Networks-on-Chip on multi-FPGA platforms |
| title_short | Rapid prototyping of Networks-on-Chip on multi-FPGA platforms |
| title_sort | rapid prototyping of networks on chip on multi fpga platforms |
| url | http://dx.doi.org/10.1051/matecconf/20165412002 |
| work_keys_str_mv | AT tanjunyan rapidprototypingofnetworksonchiponmultifpgaplatforms AT fressevirginie rapidprototypingofnetworksonchiponmultifpgaplatforms AT rousseaufrederic rapidprototypingofnetworksonchiponmultifpgaplatforms |