Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations
Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9730906/ |
| _version_ | 1811244845898924032 |
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| author | Kumar Sambhav Pandey Hitesh Shrimali |
| author_facet | Kumar Sambhav Pandey Hitesh Shrimali |
| author_sort | Kumar Sambhav Pandey |
| collection | DOAJ |
| description | Parallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM). |
| first_indexed | 2024-04-12T14:31:54Z |
| format | Article |
| id | doaj.art-e3473fdebd7b4e768a11642d1f663c2e |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-12T14:31:54Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-e3473fdebd7b4e768a11642d1f663c2e2022-12-22T03:29:15ZengIEEEIEEE Access2169-35362022-01-0110569855699510.1109/ACCESS.2022.31578799730906Novel VLSI Architectures and Micro-Cell Libraries for Subscalar ComputationsKumar Sambhav Pandey0https://orcid.org/0000-0003-2840-3939Hitesh Shrimali1https://orcid.org/0000-0003-2776-1005Department of Electronics and Communication Engineering, National Institute of Technology Hamirpur, Hamirpur, IndiaSchool of Computing and Electrical Engineering, Indian Institute of Technology Mandi, Mandi, IndiaParallelism is the key to enhancing the throughput of computing structures. However, it is well established that the presence of data-flow dependencies adversely impacts the exploitation of such parallelism. This paper presents a case for a new computing paradigm namely subscalar digital arithmetic which is aimed at mitigating this issue. It proposes to break up atomic data and atomic operations thereon into sub-atomic data fragments and sub-atomic partial operations. Such a break-up exposes hitherto unexploited levels of parallelism by way of allowing overlap of operations even if data-dependent. Surprisingly this enhanced exploitation of latent parallelism comes with a favorable impact on the area-power characteristics of corresponding computing structures which is contrary to common sense. The paper also proposes a novel micro cell library with logic primitives at corresponding subscalar levels. The synthesized circuits for several sequential benchmarks show an order of magnitude improvement in their area-throughput figure-of-merit (FOM).https://ieeexplore.ieee.org/document/9730906/Bit-level parallelismdigital arithmeticpipelining |
| spellingShingle | Kumar Sambhav Pandey Hitesh Shrimali Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations IEEE Access Bit-level parallelism digital arithmetic pipelining |
| title | Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations |
| title_full | Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations |
| title_fullStr | Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations |
| title_full_unstemmed | Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations |
| title_short | Novel VLSI Architectures and Micro-Cell Libraries for Subscalar Computations |
| title_sort | novel vlsi architectures and micro cell libraries for subscalar computations |
| topic | Bit-level parallelism digital arithmetic pipelining |
| url | https://ieeexplore.ieee.org/document/9730906/ |
| work_keys_str_mv | AT kumarsambhavpandey novelvlsiarchitecturesandmicrocelllibrariesforsubscalarcomputations AT hiteshshrimali novelvlsiarchitecturesandmicrocelllibrariesforsubscalarcomputations |