Instruction-level Real-time Secure Processor Using an Error Correction Code

In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated u...

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Main Authors: YOON, S. M., LEE, S. W., PARK, J. K., KIM, J. T.
Format: Article
Language:English
Published: Stefan cel Mare University of Suceava 2015-08-01
Series:Advances in Electrical and Computer Engineering
Subjects:
Online Access:http://dx.doi.org/10.4316/AECE.2015.03002
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author YOON, S. M.
LEE, S. W.
PARK, J. K.
KIM, J. T.
author_facet YOON, S. M.
LEE, S. W.
PARK, J. K.
KIM, J. T.
author_sort YOON, S. M.
collection DOAJ
description In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area.
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spelling doaj.art-e436d8224112408bbca305e7fc49b4e62022-12-21T17:57:30ZengStefan cel Mare University of SuceavaAdvances in Electrical and Computer Engineering1582-74451844-76002015-08-01153131610.4316/AECE.2015.03002Instruction-level Real-time Secure Processor Using an Error Correction CodeYOON, S. M.LEE, S. W.PARK, J. K.KIM, J. T.In this paper, we present a processor that detects security-attacks at the instruction level by checking the integrity of instructions in real time. To confirm the integrity of the instructions, we generate a parity chain of instructions and check them at run time. The parity chain is generated using an error correction code used in a digital communication system, and the integrity checker has the same function as the error-detector module of the error correction code. This architecture can readily be applied to a general processor, because the checker is located between the processor core and the instruction memory. Compared with other cipher modules with the same key space, our instruction integrity checker achieves a faster check speed and occupies a smaller area.http://dx.doi.org/10.4316/AECE.2015.03002secure processorsecurityinstructioncorrelationchain
spellingShingle YOON, S. M.
LEE, S. W.
PARK, J. K.
KIM, J. T.
Instruction-level Real-time Secure Processor Using an Error Correction Code
Advances in Electrical and Computer Engineering
secure processor
security
instruction
correlation
chain
title Instruction-level Real-time Secure Processor Using an Error Correction Code
title_full Instruction-level Real-time Secure Processor Using an Error Correction Code
title_fullStr Instruction-level Real-time Secure Processor Using an Error Correction Code
title_full_unstemmed Instruction-level Real-time Secure Processor Using an Error Correction Code
title_short Instruction-level Real-time Secure Processor Using an Error Correction Code
title_sort instruction level real time secure processor using an error correction code
topic secure processor
security
instruction
correlation
chain
url http://dx.doi.org/10.4316/AECE.2015.03002
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AT kimjt instructionlevelrealtimesecureprocessorusinganerrorcorrectioncode