Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET)
Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar cu...
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-03-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/10/4/229 |
| _version_ | 1818991717913722880 |
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| author | Hwa Young Gu Sangwan Kim |
| author_facet | Hwa Young Gu Sangwan Kim |
| author_sort | Hwa Young Gu |
| collection | DOAJ |
| description | Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (<i>I</i><sub>AMB</sub>). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (<i>I</i><sub>ON</sub>), <i>I</i><sub>AMB</sub>, and gate-to-drain capacitance (<i>C</i><sub>GD</sub>). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot. |
| first_indexed | 2024-12-20T20:14:43Z |
| format | Article |
| id | doaj.art-e5352110aae14d3aa4bd93d025ae62f0 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-12-20T20:14:43Z |
| publishDate | 2019-03-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-e5352110aae14d3aa4bd93d025ae62f02022-12-21T19:27:45ZengMDPI AGMicromachines2072-666X2019-03-0110422910.3390/mi10040229mi10040229Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET)Hwa Young Gu0Sangwan Kim1Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, KoreaDepartment of Electrical and Computer Engineering, Ajou University, Suwon 16499, KoreaRecently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-power semi-conductor devices. To commercialize the TFETs, however, it is necessary to improve an on-state current caused by tunnel-junction resistance and to suppress a leakage current from ambipolar current (<i>I</i><sub>AMB</sub>). In this paper, we suggest a novel TFET which features double gate, vertical, and trapezoid isosceles channel structure to solve the above-mentioned technical issues. The device design is optimized by examining its electrical characteristics with the help of technology computer-aided design (TCAD) simulation. As a result, double-gate isosceles trapezoid (DGIT) TFET shows a much better performance than the conventional TFET in terms of ON-state current (<i>I</i><sub>ON</sub>), <i>I</i><sub>AMB</sub>, and gate-to-drain capacitance (<i>C</i><sub>GD</sub>). It is confirmed that an inverter composed of DGIT-TFETs can operate with less than 1 ns intrinsic delay time and negligible voltage overshoot.https://www.mdpi.com/2072-666X/10/4/229tunnel field-effect transistors (TFETs)ambipolar currentscalingsubthreshold swingFinFET |
| spellingShingle | Hwa Young Gu Sangwan Kim Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET) Micromachines tunnel field-effect transistors (TFETs) ambipolar current scaling subthreshold swing FinFET |
| title | Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET) |
| title_full | Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET) |
| title_fullStr | Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET) |
| title_full_unstemmed | Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET) |
| title_short | Design Optimization of Double-Gate Isosceles Trapezoid Tunnel Field-Effect Transistor (DGIT-TFET) |
| title_sort | design optimization of double gate isosceles trapezoid tunnel field effect transistor dgit tfet |
| topic | tunnel field-effect transistors (TFETs) ambipolar current scaling subthreshold swing FinFET |
| url | https://www.mdpi.com/2072-666X/10/4/229 |
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