Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography
In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduc...
| Main Authors: | , , , , |
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| Format: | Article |
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IEEE
2020-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9069237/ |
| _version_ | 1818854859650105344 |
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| author | MD. Mainul Islam MD. Selim Hossain MD. Shahjalal MOH. Khalid Hasan Yeong Min Jang |
| author_facet | MD. Mainul Islam MD. Selim Hossain MD. Shahjalal MOH. Khalid Hasan Yeong Min Jang |
| author_sort | MD. Mainul Islam |
| collection | DOAJ |
| description | In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication. |
| first_indexed | 2024-12-19T07:59:24Z |
| format | Article |
| id | doaj.art-e7d824d2e2c6426eb726621a9c5159da |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-19T07:59:24Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-e7d824d2e2c6426eb726621a9c5159da2022-12-21T20:29:55ZengIEEEIEEE Access2169-35362020-01-018738987390610.1109/ACCESS.2020.29883799069237Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve CryptographyMD. Mainul Islam0https://orcid.org/0000-0002-9686-5994MD. Selim Hossain1https://orcid.org/0000-0003-3754-3618MD. Shahjalal2https://orcid.org/0000-0002-4876-6860MOH. Khalid Hasan3https://orcid.org/0000-0002-7773-3523Yeong Min Jang4https://orcid.org/0000-0003-1487-086XDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDepartment of Electrical and Electronic Engineering, Khulna University of Engineering & Technology, Khulna, BangladeshDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaDepartment of Electronics Engineering, Kookmin University, Seoul, South KoreaIn this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.https://ieeexplore.ieee.org/document/9069237/Modular multiplicationinterleaved multiplicationelliptic curve cryptography |
| spellingShingle | MD. Mainul Islam MD. Selim Hossain MD. Shahjalal MOH. Khalid Hasan Yeong Min Jang Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography IEEE Access Modular multiplication interleaved multiplication elliptic curve cryptography |
| title | Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography |
| title_full | Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography |
| title_fullStr | Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography |
| title_full_unstemmed | Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography |
| title_short | Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography |
| title_sort | area time efficient hardware implementation of modular multiplication for elliptic curve cryptography |
| topic | Modular multiplication interleaved multiplication elliptic curve cryptography |
| url | https://ieeexplore.ieee.org/document/9069237/ |
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