Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA
There are two methods to implement LUT up to 7-bit depends on the type of Xilinx chip hardware and the software that can use in design and the code generation. The first method implements LUT as a RAM. This method gives high speed and requires a very high cost.The second method implements LUT as lo...
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| Format: | Article |
| Language: | Arabic |
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Mustansiriyah University/College of Engineering
2005-06-01
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| Series: | Journal of Engineering and Sustainable Development |
| Subjects: | |
| Online Access: | https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1848 |
| _version_ | 1798022542943846400 |
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| author | Dhafer R. Zaghar Khamis A. Zidan Laiyth M. Al-Rawi |
| author_facet | Dhafer R. Zaghar Khamis A. Zidan Laiyth M. Al-Rawi |
| author_sort | Dhafer R. Zaghar |
| collection | DOAJ |
| description |
There are two methods to implement LUT up to 7-bit depends on the type of Xilinx chip hardware and the software that can use in design and the code generation. The first method implements LUT as a RAM. This method gives high speed and requires a very high cost.The second method implements LUT as logic gates. This method requires special software and gives a low speed implies. This paper proposed a modification to the second method that will save the speed of the first method and low cost of the second method. It depends on the design of the LUT. Therefore it will not require special software.
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| first_indexed | 2024-04-11T17:31:45Z |
| format | Article |
| id | doaj.art-e9af8a1abf7449d6a30a2c156f740b1e |
| institution | Directory Open Access Journal |
| issn | 2520-0917 2520-0925 |
| language | Arabic |
| last_indexed | 2024-04-11T17:31:45Z |
| publishDate | 2005-06-01 |
| publisher | Mustansiriyah University/College of Engineering |
| record_format | Article |
| series | Journal of Engineering and Sustainable Development |
| spelling | doaj.art-e9af8a1abf7449d6a30a2c156f740b1e2022-12-22T04:12:01ZaraMustansiriyah University/College of EngineeringJournal of Engineering and Sustainable Development2520-09172520-09252005-06-0192Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGADhafer R. Zaghar0Khamis A. Zidan1Laiyth M. Al-Rawi2Computer & Software Eng. Dept., College of Eng., Al-Mustansiriya University, Baghdad, IraqComputer & Software Eng. Dept., College of Eng., Al-Mustansiriya University, Baghdad, IraqComputer & Software Eng. Dept., College of Eng., Al-Mustansiriya University, Baghdad, Iraq There are two methods to implement LUT up to 7-bit depends on the type of Xilinx chip hardware and the software that can use in design and the code generation. The first method implements LUT as a RAM. This method gives high speed and requires a very high cost.The second method implements LUT as logic gates. This method requires special software and gives a low speed implies. This paper proposed a modification to the second method that will save the speed of the first method and low cost of the second method. It depends on the design of the LUT. Therefore it will not require special software. https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1848zero |
| spellingShingle | Dhafer R. Zaghar Khamis A. Zidan Laiyth M. Al-Rawi Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA Journal of Engineering and Sustainable Development zero |
| title | Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA |
| title_full | Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA |
| title_fullStr | Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA |
| title_full_unstemmed | Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA |
| title_short | Low Cost and High Speed Look-Up Table Implementation of Xilinx FPGA |
| title_sort | low cost and high speed look up table implementation of xilinx fpga |
| topic | zero |
| url | https://jeasd.uomustansiriyah.edu.iq/index.php/jeasd/article/view/1848 |
| work_keys_str_mv | AT dhaferrzaghar lowcostandhighspeedlookuptableimplementationofxilinxfpga AT khamisazidan lowcostandhighspeedlookuptableimplementationofxilinxfpga AT laiythmalrawi lowcostandhighspeedlookuptableimplementationofxilinxfpga |