Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory
The memory cell density and memory capacity have been increased for obtaining larger and faster memory. However, this threatens the memory reliability by increasing the probability of faulty cell generation. In this paper, a fast and small-area built-in redundancy analysis (RA) for the post-bond rep...
Main Authors: | Donghyun Han, Hayoung Lee, Sungho Kang |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2021-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9439471/ |
Similar Items
-
Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC
by: Suleman Alnatheer, et al.
Published: (2021-07-01) -
Deep Q-Learning with Bit-Swapping-Based Linear Feedback Shift Register fostered Built-In Self-Test and Built-In Self-Repair for SRAM
by: Mohammed Altaf Ahmed, et al.
Published: (2022-06-01) -
A Novel Built-In Self-Repair Scheme for 3D Memory
by: Tianming Ni, et al.
Published: (2019-01-01) -
On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug
by: Hayoung Lee, et al.
Published: (2021-01-01) -
Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC’s
by: Renold Sam Vethamuthu Edward Alaises, et al.
Published: (2023-02-01)