FPGA Prototyping of RNN Decoder for Convolutional Codes
<p/> <p>This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
SpringerOpen
2006-01-01
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| Series: | EURASIP Journal on Advances in Signal Processing |
| Online Access: | http://dx.doi.org/10.1155/ASP/2006/15640 |
| Summary: | <p/> <p>This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA), thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.</p> |
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| ISSN: | 1687-6172 1687-6180 |