FPGA Prototyping of RNN Decoder for Convolutional Codes

FPGA Prototyping of RNN Decoder for Convolutional Codes

<p/> <p>This paper presents prototyping of a recurrent type neural network (RNN) convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that...

Full description

Bibliographic Details
Main Authors: Salcic Zoran, Berber Stevan, Secker Paul
Format: Article
Language:English
Published: SpringerOpen 2006-01-01
Series:EURASIP Journal on Advances in Signal Processing
Online Access:http://dx.doi.org/10.1155/ASP/2006/15640

Similar Items

Similar Items