Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization
As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from last level cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the ca...
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| Format: | Article |
| Language: | English |
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IEEE
2018-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8308725/ |
| _version_ | 1819168438612918272 |
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| author | Navid Khoshavi Ronald F. Demara |
| author_facet | Navid Khoshavi Ronald F. Demara |
| author_sort | Navid Khoshavi |
| collection | DOAJ |
| description | As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from last level cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this paper concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with spin-transfer torque random access memory (STT-MRAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique improves the temporal locality while preventing cache thrashing via sufficient accommodation of the frequently read reused fraction of working set that may exhibit distant re-reference interval in L2. Our experimental results show that the proposed technique can reduce the L2 read miss ratio by 51.7% on average compared to conventional STT-MRAM L2 design across PARSEC and SPEC2006 workloads while significantly decreasing the L2 dynamic energy consumption. |
| first_indexed | 2024-12-22T19:03:37Z |
| format | Article |
| id | doaj.art-ec1d954b4af148c4a423cc12bf3bd0f3 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-22T19:03:37Z |
| publishDate | 2018-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-ec1d954b4af148c4a423cc12bf3bd0f32022-12-21T18:15:52ZengIEEEIEEE Access2169-35362018-01-016145761459010.1109/ACCESS.2018.28136688308725Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy OptimizationNavid Khoshavi0https://orcid.org/0000-0002-4010-1354Ronald F. Demara1Department of Computer Science, Florida Polytechnic University, Lakeland, FL, USADepartment of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USAAs capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from last level cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval while waiting to access the data stored in the cache blocks in LLC, if there are no independent instructions to execute. To provide accelerated service to the critical loads requests from LLC, this paper concentrates on leveraging the additional capacity offered by replacing SRAM-based L2 with spin-transfer torque random access memory (STT-MRAM) to accommodate frequently accessed cache blocks in exclusive read mode in favor of reducing the overall read service time. Our proposed technique improves the temporal locality while preventing cache thrashing via sufficient accommodation of the frequently read reused fraction of working set that may exhibit distant re-reference interval in L2. Our experimental results show that the proposed technique can reduce the L2 read miss ratio by 51.7% on average compared to conventional STT-MRAM L2 design across PARSEC and SPEC2006 workloads while significantly decreasing the L2 dynamic energy consumption.https://ieeexplore.ieee.org/document/8308725/Non-volatile memorySTT-MRAM retention relaxationlast level cacheenergy overhead reductionread service timecritical loads |
| spellingShingle | Navid Khoshavi Ronald F. Demara Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization IEEE Access Non-volatile memory STT-MRAM retention relaxation last level cache energy overhead reduction read service time critical loads |
| title | Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization |
| title_full | Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization |
| title_fullStr | Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization |
| title_full_unstemmed | Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization |
| title_short | Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization |
| title_sort | read tuned stt ram and edram cache hierarchies for throughput and energy optimization |
| topic | Non-volatile memory STT-MRAM retention relaxation last level cache energy overhead reduction read service time critical loads |
| url | https://ieeexplore.ieee.org/document/8308725/ |
| work_keys_str_mv | AT navidkhoshavi readtunedsttramandedramcachehierarchiesforthroughputandenergyoptimization AT ronaldfdemara readtunedsttramandedramcachehierarchiesforthroughputandenergyoptimization |