Hardware Implementation of IP Packet Filtering in FPGA
In the present rapid expansion of the number of computers and devices connected to the Internet, one of the top three issues that need to be addressed is the network security. The greater the number of connected users and devices, the attempts to invade privacy and data of connected users becomes mo...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Anhalt University of Applied Sciences
2019-03-01
|
| Series: | Proceedings of the International Conference on Applied Innovations in IT |
| Subjects: | |
| Online Access: | https://icaiit.org/paper.php?paper=7th_ICAIIT_1/1_5 |
| _version_ | 1797815338069393408 |
|---|---|
| author | Ana Cholakoska Danijela Efnusheva Marija Kalendar |
| author_facet | Ana Cholakoska Danijela Efnusheva Marija Kalendar |
| author_sort | Ana Cholakoska |
| collection | DOAJ |
| description | In the present rapid expansion of the number of computers and devices connected to the Internet, one of the top three issues that need to be addressed is the network security. The greater the number of connected users and devices, the attempts to invade privacy and data of connected users becomes more and more tempting to hostile users. Thus, network intrusion detection systems become more and more necessary and present in any network enabling Internet connections. This paper addresses the network security issues by implementing NIDS style hardware implementation for filtering network packets intended for faster packet processing and filtering. The hardware is based on several NIDS rules that can be programmed in the system's memory, thus enabling modularity and flexibility. The designed hardware modules are described in VHDL and implemented in a Virtex7 VC709 FPGA board. The results are discussed and analyzed in the paper and are presenting good foundation for further improvement. |
| first_indexed | 2024-03-13T08:21:11Z |
| format | Article |
| id | doaj.art-edb507a9fa92470a9e4937007d2cecf0 |
| institution | Directory Open Access Journal |
| issn | 2199-8876 |
| language | English |
| last_indexed | 2024-03-13T08:21:11Z |
| publishDate | 2019-03-01 |
| publisher | Anhalt University of Applied Sciences |
| record_format | Article |
| series | Proceedings of the International Conference on Applied Innovations in IT |
| spelling | doaj.art-edb507a9fa92470a9e4937007d2cecf02023-05-31T09:33:07ZengAnhalt University of Applied SciencesProceedings of the International Conference on Applied Innovations in IT2199-88762019-03-0171232910.25673/13478Hardware Implementation of IP Packet Filtering in FPGAAna Cholakoska0Danijela Efnusheva1https://orcid.org/0000-0002-6069-1865Marija Kalendar2https://orcid.org/0000-0002-4226-0690Computer Science and Engineering Department, Faculty of Electrical Engineering and Information Technologies, Ss. Cyril and Methodius University, Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaComputer Science and Engineering Department, Faculty of Electrical Engineering and Information Technologies, Ss. Cyril and Methodius University, Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaComputer Science and Engineering Department, Faculty of Electrical Engineering and Information Technologies, Ss. Cyril and Methodius University, Karpos II bb, PO Box 574, 1000 Skopje, MacedoniaIn the present rapid expansion of the number of computers and devices connected to the Internet, one of the top three issues that need to be addressed is the network security. The greater the number of connected users and devices, the attempts to invade privacy and data of connected users becomes more and more tempting to hostile users. Thus, network intrusion detection systems become more and more necessary and present in any network enabling Internet connections. This paper addresses the network security issues by implementing NIDS style hardware implementation for filtering network packets intended for faster packet processing and filtering. The hardware is based on several NIDS rules that can be programmed in the system's memory, thus enabling modularity and flexibility. The designed hardware modules are described in VHDL and implemented in a Virtex7 VC709 FPGA board. The results are discussed and analyzed in the paper and are presenting good foundation for further improvement.https://icaiit.org/paper.php?paper=7th_ICAIIT_1/1_5fpgaip header fields extractingip packet filteringnetwork ids systems |
| spellingShingle | Ana Cholakoska Danijela Efnusheva Marija Kalendar Hardware Implementation of IP Packet Filtering in FPGA Proceedings of the International Conference on Applied Innovations in IT fpga ip header fields extracting ip packet filtering network ids systems |
| title | Hardware Implementation of IP Packet Filtering in FPGA |
| title_full | Hardware Implementation of IP Packet Filtering in FPGA |
| title_fullStr | Hardware Implementation of IP Packet Filtering in FPGA |
| title_full_unstemmed | Hardware Implementation of IP Packet Filtering in FPGA |
| title_short | Hardware Implementation of IP Packet Filtering in FPGA |
| title_sort | hardware implementation of ip packet filtering in fpga |
| topic | fpga ip header fields extracting ip packet filtering network ids systems |
| url | https://icaiit.org/paper.php?paper=7th_ICAIIT_1/1_5 |
| work_keys_str_mv | AT anacholakoska hardwareimplementationofippacketfilteringinfpga AT danijelaefnusheva hardwareimplementationofippacketfilteringinfpga AT marijakalendar hardwareimplementationofippacketfilteringinfpga |