Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking
In triple-well PMOSFET transistor, a deep n+ well (DNW) is a process used to isolate the substrate noise, which can lead to changes in effect of single event transient (SET). In outer space, collision of cosmic energetic particles with sensitive nodes of integrated circuits can generate electron-hol...
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IEEE
2019-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/8862954/ |
| _version_ | 1818737150804361216 |
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| author | Jizuo Zhang Liang Fang Jianjun Chen Shen Hou Xianyu Tong |
| author_facet | Jizuo Zhang Liang Fang Jianjun Chen Shen Hou Xianyu Tong |
| author_sort | Jizuo Zhang |
| collection | DOAJ |
| description | In triple-well PMOSFET transistor, a deep n+ well (DNW) is a process used to isolate the substrate noise, which can lead to changes in effect of single event transient (SET). In outer space, collision of cosmic energetic particles with sensitive nodes of integrated circuits can generate electron-hole pairs. The probability of recombination of electrons and holes is different, which results in transient changes of sensitive nodes' state. Transient potential change is transmitted to the output terminal, that is, a single event transient. In this paper, measured SET effect characteristics of PMOSFET transistors in 65 nm process are performed with heavy particle experiments. Compared with triple-well PMOSFET transistor, the experimental data show that the average of SET pulse width in double-well PMOSFET is increased by 19.4% (Ge linear energy transfer (LET) = 37.4 MeV · cm2/mg) and 14.4% (Ti LET = 22.2 MeV · cm<sup>2</sup>/mg). The data show that a triple-well PMOSFET transistor is better for SET, which is be appropriate for radiation hardened integrated circuits (ICs) design. |
| first_indexed | 2024-12-18T00:48:28Z |
| format | Article |
| id | doaj.art-ef90701d9a2040d392fa850c26dd764e |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-18T00:48:28Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj.art-ef90701d9a2040d392fa850c26dd764e2022-12-21T21:26:44ZengIEEEIEEE Access2169-35362019-01-01714925514926110.1109/ACCESS.2019.29462138862954Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle StrikingJizuo Zhang0https://orcid.org/0000-0003-3514-9035Liang Fang1Jianjun Chen2Shen Hou3https://orcid.org/0000-0001-7525-2825Xianyu Tong4Institute for Quantum Information College of Computer, National University of Defense Technology, Changsha, ChinaInstitute for Quantum Information College of Computer, National University of Defense Technology, Changsha, ChinaInstitute for Quantum Information College of Computer, National University of Defense Technology, Changsha, ChinaInstitute for Quantum Information College of Computer, National University of Defense Technology, Changsha, ChinaInstitute for Quantum Information College of Computer, National University of Defense Technology, Changsha, ChinaIn triple-well PMOSFET transistor, a deep n+ well (DNW) is a process used to isolate the substrate noise, which can lead to changes in effect of single event transient (SET). In outer space, collision of cosmic energetic particles with sensitive nodes of integrated circuits can generate electron-hole pairs. The probability of recombination of electrons and holes is different, which results in transient changes of sensitive nodes' state. Transient potential change is transmitted to the output terminal, that is, a single event transient. In this paper, measured SET effect characteristics of PMOSFET transistors in 65 nm process are performed with heavy particle experiments. Compared with triple-well PMOSFET transistor, the experimental data show that the average of SET pulse width in double-well PMOSFET is increased by 19.4% (Ge linear energy transfer (LET) = 37.4 MeV · cm2/mg) and 14.4% (Ti LET = 22.2 MeV · cm<sup>2</sup>/mg). The data show that a triple-well PMOSFET transistor is better for SET, which is be appropriate for radiation hardened integrated circuits (ICs) design.https://ieeexplore.ieee.org/document/8862954/Particledeep n+ well (DNW)PN junction |
| spellingShingle | Jizuo Zhang Liang Fang Jianjun Chen Shen Hou Xianyu Tong Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking IEEE Access Particle deep n+ well (DNW) PN junction |
| title | Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking |
| title_full | Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking |
| title_fullStr | Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking |
| title_full_unstemmed | Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking |
| title_short | Single Event Transient Study of pMOS Transistors in 65 nm Technology With and Without a Deep n+ Well Under Particle Striking |
| title_sort | single event transient study of pmos transistors in 65 nm technology with and without a deep n x002b well under particle striking |
| topic | Particle deep n+ well (DNW) PN junction |
| url | https://ieeexplore.ieee.org/document/8862954/ |
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