Utilizing block size variability to enhance instruction fetch rate
In the past, instruction fetch speeds have been improved by using cache schemes that capture the actual program flow. In this paper, we elaborate on the architecture and operation of an instruction cache named Variable-Sized Block Cache (VSBC) that also makes use of the dynamic behavior of a program...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata
2007-04-01
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| Series: | Journal of Computer Science and Technology |
| Subjects: | |
| Online Access: | https://journal.info.unlp.edu.ar/JCST/article/view/786 |