A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme
A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpo...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-07-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/12/15/7674 |
| _version_ | 1797414627207806976 |
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| author | Guangbo Xu Bingting Zha Tuanjie Xia Zhen Zheng He Zhang |
| author_facet | Guangbo Xu Bingting Zha Tuanjie Xia Zhen Zheng He Zhang |
| author_sort | Guangbo Xu |
| collection | DOAJ |
| description | A novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs. |
| first_indexed | 2024-03-09T05:36:09Z |
| format | Article |
| id | doaj.art-f188c6db10d7450ab359189d99568a6c |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-09T05:36:09Z |
| publishDate | 2022-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-f188c6db10d7450ab359189d99568a6c2023-12-03T12:28:38ZengMDPI AGApplied Sciences2076-34172022-07-011215767410.3390/app12157674A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation SchemeGuangbo Xu0Bingting Zha1Tuanjie Xia2Zhen Zheng3He Zhang4School of Mechanical Engineering, Nanjing University of Science and Technology, Nanjing 210094, ChinaSchool of Mechanical Engineering, Nanjing University of Science and Technology, Nanjing 210094, ChinaShanghai Aerospace Control Technology Institute, Shanghai 201109, ChinaSchool of Mechanical Engineering, Nanjing University of Science and Technology, Nanjing 210094, ChinaSchool of Mechanical Engineering, Nanjing University of Science and Technology, Nanjing 210094, ChinaA novel ring oscillator-based Vernier-type time interpolation method, known as the fine-timestamp maker, is proposed for field programmable gate array (FPGA)-based time-to-digital converters (TDCs). This method determines lower measurement dead time and improves resolution by using a bi-time interpolation scheme, first presented in this paper. Additionally, a group of cascaded delay units are packaged as an intellectual property core (DU-IP) to form a ring delay line and to adjust its length via the engineering change order (ECO) tool, which makes the adjustment of the ring oscillator’s frequency more linear and less position dependent. A prototype TDC was implemented on a Kintex-7 FPGA. The experimental results demonstrate that a single TDC channel only consumes 35 DFFs, 31 LUTs, and 16 CARRY4 logics after specific adjustment. The results, with a time resolution of 20 ps, dead time of 58 ns, and a root-mean-square error of 15–20 ps, show a significant performance improvement compared to traditional Vernier-type TDCs.https://www.mdpi.com/2076-3417/12/15/7674time-to-digital converterFPGAVernierhigh precisionhigh throughputIP core |
| spellingShingle | Guangbo Xu Bingting Zha Tuanjie Xia Zhen Zheng He Zhang A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme Applied Sciences time-to-digital converter FPGA Vernier high precision high throughput IP core |
| title | A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme |
| title_full | A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme |
| title_fullStr | A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme |
| title_full_unstemmed | A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme |
| title_short | A High-Throughput Vernier Time-to-Digital Converter on FPGAs with Improved Resolution Using a Bi-Time Interpolation Scheme |
| title_sort | high throughput vernier time to digital converter on fpgas with improved resolution using a bi time interpolation scheme |
| topic | time-to-digital converter FPGA Vernier high precision high throughput IP core |
| url | https://www.mdpi.com/2076-3417/12/15/7674 |
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