Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency
Cryptographic devices in hostile environments can be vulnerable to physical attacks such as power analysis. Masking is a popular countermeasure against such attacks, which works by splitting every sensitive variable into d+1 randomized shares. The implementation cost of the masking countermeasure i...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Ruhr-Universität Bochum
2023-12-01
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| Series: | Transactions on Cryptographic Hardware and Embedded Systems |
| Subjects: | |
| Online Access: | https://tches.iacr.org/index.php/TCHES/article/view/11254 |
| _version_ | 1827595095840391168 |
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| author | Barbara Gigerl Franz Klug Stefan Mangard Florian Mendel Robert Primas |
| author_facet | Barbara Gigerl Franz Klug Stefan Mangard Florian Mendel Robert Primas |
| author_sort | Barbara Gigerl |
| collection | DOAJ |
| description |
Cryptographic devices in hostile environments can be vulnerable to physical attacks such as power analysis. Masking is a popular countermeasure against such attacks, which works by splitting every sensitive variable into d+1 randomized shares. The implementation cost of the masking countermeasure in hardware increases significantly with the masking order d, and protecting designs often results in a large overhead. One of the main drivers of the cost is the required amount of fresh randomness for masking the non-linear parts of a cipher. In the case of AES, first-order designs have been built without the need for any fresh randomness, but state-of-the-art higher-order designs still require a significant number of random bits per encryption. Attempts to reduce the randomness however often result in a considerable latency overhead, which is not favorable in practice. This raises the need for AES designs offering a decent performance tradeoff, which are efficient both in terms of required randomness and latency.
In this work, we present a second-order AES design with the minimal number of three shares, requiring only 3 200 random bits per encryption at a latency of 5 cycles per round. Our design represents a significant improvement compared to state-of-the-art designs that require more randomness and/or have a higher latency. The core of the design is an optimized 5-cycle AES S-box which needs 78 bits of fresh randomness. We use this S-box to construct a round-based AES design, for which we present a concept for sharing randomness across the S-boxes based on the changing of the guards (COTG) technique. We assess the security of our design in the probing model using a formal verification tool. Furthermore, we evaluate the practical side-channel resistance on an FPGA.
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| first_indexed | 2024-03-09T02:46:52Z |
| format | Article |
| id | doaj.art-f19312cb55264a7c82025e85e6969510 |
| institution | Directory Open Access Journal |
| issn | 2569-2925 |
| language | English |
| last_indexed | 2024-03-09T02:46:52Z |
| publishDate | 2023-12-01 |
| publisher | Ruhr-Universität Bochum |
| record_format | Article |
| series | Transactions on Cryptographic Hardware and Embedded Systems |
| spelling | doaj.art-f19312cb55264a7c82025e85e69695102023-12-05T16:13:00ZengRuhr-Universität BochumTransactions on Cryptographic Hardware and Embedded Systems2569-29252023-12-012024110.46586/tches.v2024.i1.309-335Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low LatencyBarbara Gigerl0Franz Klug1Stefan Mangard2Florian Mendel3Robert Primas4Graz University of Technology, Graz, AustriaInfineon Technologies AG, Munich, GermanyGraz University of Technology, Graz, AustriaInfineon Technologies AG, Munich, GermanyIntel Labs, Hillsboro, USA Cryptographic devices in hostile environments can be vulnerable to physical attacks such as power analysis. Masking is a popular countermeasure against such attacks, which works by splitting every sensitive variable into d+1 randomized shares. The implementation cost of the masking countermeasure in hardware increases significantly with the masking order d, and protecting designs often results in a large overhead. One of the main drivers of the cost is the required amount of fresh randomness for masking the non-linear parts of a cipher. In the case of AES, first-order designs have been built without the need for any fresh randomness, but state-of-the-art higher-order designs still require a significant number of random bits per encryption. Attempts to reduce the randomness however often result in a considerable latency overhead, which is not favorable in practice. This raises the need for AES designs offering a decent performance tradeoff, which are efficient both in terms of required randomness and latency. In this work, we present a second-order AES design with the minimal number of three shares, requiring only 3 200 random bits per encryption at a latency of 5 cycles per round. Our design represents a significant improvement compared to state-of-the-art designs that require more randomness and/or have a higher latency. The core of the design is an optimized 5-cycle AES S-box which needs 78 bits of fresh randomness. We use this S-box to construct a round-based AES design, for which we present a concept for sharing randomness across the S-boxes based on the changing of the guards (COTG) technique. We assess the security of our design in the probing model using a formal verification tool. Furthermore, we evaluate the practical side-channel resistance on an FPGA. https://tches.iacr.org/index.php/TCHES/article/view/11254MaskingAESOpenTitanVerificationHardware |
| spellingShingle | Barbara Gigerl Franz Klug Stefan Mangard Florian Mendel Robert Primas Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency Transactions on Cryptographic Hardware and Embedded Systems Masking AES OpenTitan Verification Hardware |
| title | Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency |
| title_full | Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency |
| title_fullStr | Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency |
| title_full_unstemmed | Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency |
| title_short | Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency |
| title_sort | smooth passage with the guards second order hardware masking of the aes with low randomness and low latency |
| topic | Masking AES OpenTitan Verification Hardware |
| url | https://tches.iacr.org/index.php/TCHES/article/view/11254 |
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