A new Dual-Vt 4T SRAM bitcell design - Zhang Luxuan; Qiao Shushan; Hao Xudan (Dianzi Jishu Yingyong, 2018)
Reducing the memory bit cell area by reducing the number of transistors is a relatively straightforward solution to achieving a high density SRAM design. In the design of critical SRAM cells, the stability characteristics exhibited by different operating states are important criteria for judging the SRAM design. In this paper, the stability of the data retention and read write operations of the traditional 6T and 4T SRAM cells is compared, under the 55 nm CMOS process node. After Monte Carlo simulations, the results show that compared with the 6T SRAM structure, 4T reduces the layout area by 20%. At the same power supply voltage(VDD), by adding a read assist circuit in the peripheral circuit, the read stability is increased by 110% , and the write capability is enhanced by 183%.