A new Dual-Vt 4T SRAM bitcell design

A new Dual-Vt 4T SRAM bitcell design

Reducing the memory bit cell area by reducing the number of transistors is a relatively straightforward solution to achieving a high density SRAM design. In the design of critical SRAM cells, the stability characteristics exhibited by different operating states are important criteria for judging the...

Full description

Bibliographic Details
Main Authors:	Zhang Luxuan, Qiao Shushan, Hao Xudan
Format:	Article
Language:	zho
Published:	National Computer System Engineering Research Institute of China 2018-11-01
Series:	Dianzi Jishu Yingyong
Subjects:	SRAM bit cell stability read assist circuit write capability
Online Access:	http://www.chinaaet.com/article/3000093342

Similar Items

Analyzing Sub-Threshold Bitcell Topologies and the Effects of Assist Methods on SRAM V<sub>MIN</sub>
by: James Boley, et al.
Published: (2012-04-01)

Energy-Efficient Dual-Node-Upset-Recoverable 12T SRAM for Low-Power Aerospace Applications
by: Soumitra Pal, et al.
Published: (2023-01-01)

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM
by: Kiryong Kim, et al.
Published: (2021-01-01)

Low Leakage and Robust Sub-threshold SRAM Cell Using Memristor
by: Zeba Mustaqueem, et al.
Published: (2022-12-01)

Design of low power SRAM cells with increased read and write performance using Read - Write assist technique
by: M. Srinu, et al.
Published: (2024-03-01)

Radiation hardened 12T SRAM cell with improved writing capability for space applications
by: Rishabh Sharma, et al.
Published: (2023-10-01)

Improved reliability single loop single feed 7T SRAM cell for biomedical applications
by: Ashish Panchal, et al.
Published: (2023-07-01)

A Minimum Leakage Quasi-Static RAM Bitcell
by: Adam Teman, et al.
Published: (2011-05-01)

A Comparative Study of Single- and Dual-Threshold Voltage SRAM Cells
by: Pragya Kushwaha, et al.
Published: (2023-06-01)

An Ultra-Low Energy Subthreshold SRAM Bitcell for Energy Constrained Biomedical Applications
by: Arijit Banerjee, et al.
Published: (2014-05-01)

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques
by: S. Kumar, et al.
Published: (2017-09-01)

A High-Reliability 12T SRAM Radiation-Hardened Cell for Aerospace Applications
by: Ruxue Yao, et al.
Published: (2023-06-01)

Ultra-low voltage SRAM for IoT applications
by: Cai, Yanru
Published: (2024)

Design of SRAM with CNFET based on ternary literal circuit
by: Kang Yaopeng, et al.
Published: (2018-03-01)

A Sub-Threshold 8T SRAM Macro with 12.29 nW/KB Standby Power and 6.24 pJ/access for Battery-Less IoT SoCs
by: Farah B. Yahya, et al.
Published: (2016-05-01)

Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing
by: Chen, Junchao, et al.
Published: (2016)

S²RAM: Optimization of SRAM With Memory Access Patterns
by: Woong Choi
Published: (2024-01-01)

MODELING OF MTJ AND ITS VALIDATION USING NANOSCALE MRAM BITCELL
by: CHANDRAMAULESHWAR ROY, et al.
Published: (2017-06-01)

Performance Analysis Of SRAM and Dram in Low Power Application
by: Yuvaraj S., et al.
Published: (2023-01-01)

SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology
by: Rajiv V. Joshi, et al.
Published: (2025-01-01)

Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells
by: Sebastiano Strangio, et al.
Published: (2015-01-01)

DAM SRAM CORE: An Efficient High-Speed and Low-Power CIM SRAM CORE Design for Feature Extraction Convolutional Layers in Binary Neural Networks
by: Ruiyong Zhao, et al.
Published: (2024-04-01)

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks
by: Zupei Gu, et al.
Published: (2024-01-01)

0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization
by: Do, Anh Tuan, et al.
Published: (2016)

A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities
by: Oron Chertkow, et al.
Published: (2015-06-01)

Analysis and Optimization of Defect Generation Due to Mechanical Stress in High-Density SRAM
by: Kazunari Ishimaru, et al.
Published: (2021-01-01)

A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance
by: Wang, Bo, et al.
Published: (2018)

Low Power Neural Network by Reducing SRAM Operating Voltage
by: Keisuke Kozu, et al.
Published: (2022-01-01)

Performance evaluation of SRAM design using different field effect transistors
by: C. Venkataiah, et al.
Published: (2023-01-01)

Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM
by: Ho, Weng-Geng, et al.
Published: (2016)

On Improving Reliability of SRAM-Based Physically Unclonable Functions
by: Arunkumar Vijayakumar, et al.
Published: (2017-01-01)

CNTFET-based SRAM cell design using INDEP technique
by: Mehwish Maqbool, et al.
Published: (2024-03-01)

Hardware Efficient Transposable 8T SRAM for Orthogonal Data Access
by: Dain Chon, et al.
Published: (2024-01-01)

Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations
by: G. V. Luong, et al.
Published: (2018-01-01)

Radiation tolerant capacitor-SRAM without area overhead
by: Eunju Jo, et al.
Published: (2024-08-01)

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
by: T. Nirmalraj, et al.
Published: (2021-09-01)

Exploiting Read/Write Asymmetry to Achieve Opportunistic SRAM Voltage Switching in Dual-Supply Near-Threshold Processors
by: Yunfei Gu, et al.
Published: (2018-08-01)

A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS
by: Verma, Naveen, et al.
Published: (2010)

High-Density SRAM Read Access Yield Estimation Methodology
by: Gidong Baek, et al.
Published: (2021-01-01)

SRAM based computing-in-memory for tiny machine learning
by: Gupta, Shini
Published: (2024)