Low‐leakage zero‐static power consumption analogue CMOS switch
Abstract The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without activ...
Main Authors: | , , , , |
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Format: | Article |
Language: | English |
Published: |
Wiley
2021-06-01
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Series: | Electronics Letters |
Subjects: | |
Online Access: | https://doi.org/10.1049/ell2.12177 |
Summary: | Abstract The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without active circuits, thus producing a negligible power consumption. The technique is simple, modular, robust, and reduces the leakage current down to tens of aA at room temperature using a TSMC 0.18 µm technology. |
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ISSN: | 0013-5194 1350-911X |