Low‐leakage zero‐static power consumption analogue CMOS switch

Abstract The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without activ...

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Main Authors: Giuseppe Sciortino, Alireza Mesri, Fabio Toso, Francesco Zanetto, Giorgio Ferrari
Format: Article
Language:English
Published: Wiley 2021-06-01
Series:Electronics Letters
Subjects:
Online Access:https://doi.org/10.1049/ell2.12177
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author Giuseppe Sciortino
Alireza Mesri
Fabio Toso
Francesco Zanetto
Giorgio Ferrari
author_facet Giuseppe Sciortino
Alireza Mesri
Fabio Toso
Francesco Zanetto
Giorgio Ferrari
author_sort Giuseppe Sciortino
collection DOAJ
description Abstract The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without active circuits, thus producing a negligible power consumption. The technique is simple, modular, robust, and reduces the leakage current down to tens of aA at room temperature using a TSMC 0.18 µm technology.
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spelling doaj.art-f3aa3b5a55b84990920664d39a9aae9e2023-02-22T06:36:15ZengWileyElectronics Letters0013-51941350-911X2021-06-01571350250410.1049/ell2.12177Low‐leakage zero‐static power consumption analogue CMOS switchGiuseppe Sciortino0Alireza Mesri1Fabio Toso2Francesco Zanetto3Giorgio Ferrari4Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milano 20133 ItalyDipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milano 20133 ItalyDipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milano 20133 ItalyDipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milano 20133 ItalyDipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Milano 20133 ItalyAbstract The architecture of a low‐leakage switch in complementary metal‐oxide‐semiconductor (CMOS) technology developed to implement long‐term analogue memories for low‐power applications is presented. The switch reduces the leakage current using a cascade of modified pass‐transistors without active circuits, thus producing a negligible power consumption. The technique is simple, modular, robust, and reduces the leakage current down to tens of aA at room temperature using a TSMC 0.18 µm technology.https://doi.org/10.1049/ell2.12177Analogue processing circuitsCMOS integrated circuitsAnalogue storageElectrical/electronic equipment (energy utilisation)
spellingShingle Giuseppe Sciortino
Alireza Mesri
Fabio Toso
Francesco Zanetto
Giorgio Ferrari
Low‐leakage zero‐static power consumption analogue CMOS switch
Electronics Letters
Analogue processing circuits
CMOS integrated circuits
Analogue storage
Electrical/electronic equipment (energy utilisation)
title Low‐leakage zero‐static power consumption analogue CMOS switch
title_full Low‐leakage zero‐static power consumption analogue CMOS switch
title_fullStr Low‐leakage zero‐static power consumption analogue CMOS switch
title_full_unstemmed Low‐leakage zero‐static power consumption analogue CMOS switch
title_short Low‐leakage zero‐static power consumption analogue CMOS switch
title_sort low leakage zero static power consumption analogue cmos switch
topic Analogue processing circuits
CMOS integrated circuits
Analogue storage
Electrical/electronic equipment (energy utilisation)
url https://doi.org/10.1049/ell2.12177
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AT francescozanetto lowleakagezerostaticpowerconsumptionanaloguecmosswitch
AT giorgioferrari lowleakagezerostaticpowerconsumptionanaloguecmosswitch