| Summary: | SiC MOSFETs devices with double-trench dominate the market due to their low on-resistance. However, studies on its temperature-dependent properties are not comprehensive. This work uses fast I-V and static I-V techniques to explore the location of electrons trapped in the device under moderate gate stress. Threshold voltage instability (<inline-formula> <tex-math notation="LaTeX">${\mathrm {V}}_{\mathrm {TH}}$ </tex-math></inline-formula> hysteresis and <inline-formula> <tex-math notation="LaTeX">$\Delta{\mathrm {V}}_{\mathrm {TH}}$ </tex-math></inline-formula>) and on-resistance degradation (<inline-formula> <tex-math notation="LaTeX">$\Delta{\mathrm {R}}_{\mathrm {ON}}$ </tex-math></inline-formula>) are used to characterize oxide trapping. Although the observation method is different, it can be found that the <inline-formula> <tex-math notation="LaTeX">${\mathrm {V}}_{\mathrm {TH}}$ </tex-math></inline-formula> instability and <inline-formula> <tex-math notation="LaTeX">${\mathrm {R}}_{\mathrm {ON}}$ </tex-math></inline-formula> degradation increase linearly with logarithmic time over a wide time range from <inline-formula> <tex-math notation="LaTeX">$100~\mu{\mathrm {s}}$ </tex-math></inline-formula> to 104 s, suggesting that the direct tunneling mechanism dominates the electrons trapping in the oxide near the SiO2/SiC interface. The interface trap density is <inline-formula> <tex-math notation="LaTeX">$3.8\times 10^{12}$ </tex-math></inline-formula> cm−2<inline-formula> <tex-math notation="LaTeX">$\cdot$ </tex-math></inline-formula>eV−1. In addition, a negative temperature dependence is shown in the test, and the fitting parameter <inline-formula> <tex-math notation="LaTeX">$\gamma$ </tex-math></inline-formula> from 0.16 to 0.18 indicated that these traps are concentrated in the oxide layer. These traps’ energy level at 0.68 eV below the conduction band was obtained in the recovery phase through the Arrhenius plot.
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