Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation
Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9760423/ |
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| author | Samala Jagadheesh P. Veda Bhanu J. Soumya Linga Reddy Cenkeramaddi |
| author_facet | Samala Jagadheesh P. Veda Bhanu J. Soumya Linga Reddy Cenkeramaddi |
| author_sort | Samala Jagadheesh |
| collection | DOAJ |
| description | Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and routers. Failures in NoC components diminish system efficiency and reliability. This paper proposes a Reinforcement Learning based Fault-Tolerant Routing (RL-FTR) algorithm to tackle the routing issues caused by link and router faults in the mesh-based NoC architecture. The efficiency of the proposed RL-FTR algorithm is examined using System-C based cycle-accurate NoC simulator. Simulations are carried out by increasing the number of links and router faults in various sizes of mesh. Followed by simulations, real-time functioning of the proposed RL-FTR algorithm is observed using the FPGA implementation. Results of the simulation and hardware shows that the proposed RL-FTR algorithm provides an optimal routing path from the source router to the destination router. |
| first_indexed | 2024-12-14T18:54:08Z |
| format | Article |
| id | doaj.art-f403086019124ef89630e6aadc192c59 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-14T18:54:08Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-f403086019124ef89630e6aadc192c592022-12-21T22:51:09ZengIEEEIEEE Access2169-35362022-01-0110447244473710.1109/ACCESS.2022.31689929760423Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA ImplementationSamala Jagadheesh0https://orcid.org/0000-0003-2354-3289P. Veda Bhanu1https://orcid.org/0000-0001-5663-8407J. Soumya2https://orcid.org/0000-0003-2276-1698Linga Reddy Cenkeramaddi3https://orcid.org/0000-0002-1023-2118Department of Electrical and Electronics Engineering, Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, Telangana, IndiaDepartment of Electrical and Electronics Engineering, Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, Telangana, IndiaDepartment of Electrical and Electronics Engineering, Birla Institute of Technology and Science-Pilani, Hyderabad Campus, Hyderabad, Telangana, IndiaDepartment of Information and Communication Technology, University of Agder (UiA), Grimstad, Kristiansand, NorwayNetwork-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and routers. Failures in NoC components diminish system efficiency and reliability. This paper proposes a Reinforcement Learning based Fault-Tolerant Routing (RL-FTR) algorithm to tackle the routing issues caused by link and router faults in the mesh-based NoC architecture. The efficiency of the proposed RL-FTR algorithm is examined using System-C based cycle-accurate NoC simulator. Simulations are carried out by increasing the number of links and router faults in various sizes of mesh. Followed by simulations, real-time functioning of the proposed RL-FTR algorithm is observed using the FPGA implementation. Results of the simulation and hardware shows that the proposed RL-FTR algorithm provides an optimal routing path from the source router to the destination router.https://ieeexplore.ieee.org/document/9760423/Fault-toleranceFPGAnetwork-on-chipreinforcement learningrouting |
| spellingShingle | Samala Jagadheesh P. Veda Bhanu J. Soumya Linga Reddy Cenkeramaddi Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation IEEE Access Fault-tolerance FPGA network-on-chip reinforcement learning routing |
| title | Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation |
| title_full | Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation |
| title_fullStr | Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation |
| title_full_unstemmed | Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation |
| title_short | Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation |
| title_sort | reinforcement learning based fault tolerant routing algorithm for mesh based noc and its fpga implementation |
| topic | Fault-tolerance FPGA network-on-chip reinforcement learning routing |
| url | https://ieeexplore.ieee.org/document/9760423/ |
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