Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation
Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and...
Main Authors: | Samala Jagadheesh, P. Veda Bhanu, J. Soumya, Linga Reddy Cenkeramaddi |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2022-01-01
|
Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9760423/ |
Similar Items
-
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
by: P. Veda Bhanu, et al.
Published: (2021-01-01) -
Flexible Spare Core Placement in Torus Topology Based NoCs and Its Validation on an FPGA
by: P. Veda Bhanu, et al.
Published: (2021-01-01) -
CAFT: Cost-aware and Fault-tolerant routing algorithm in 2D mesh Network-on-Chip
by: Akram Reza, et al.
Published: (2019-11-01) -
A novel buffering fault‐tolerance approach for network on chip (NoC)
by: Nima Jafarzadeh, et al.
Published: (2023-07-01) -
LightR: A Fault-Tolerant Wavelength-Routed Optical Networks-on-Chip Topology
by: Zhidan Zheng, et al.
Published: (2023-08-01)