A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications
Links able to sustain high-speed data transfer while exposed to radiation phenomena are required by several applications, including aerospace and high-energy physics experiments. To satisfy this need, this paper outlines the design of a radiation-hard line driver for communication up to 10 Gb/s. The...
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IEEE
2023-01-01
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Series: | IEEE Access |
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Online Access: | https://ieeexplore.ieee.org/document/10188687/ |
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author | Gabriele Ciarpi Marco Mestice Daniele Rossi Fabrizio Palla Sergio Saponara |
author_facet | Gabriele Ciarpi Marco Mestice Daniele Rossi Fabrizio Palla Sergio Saponara |
author_sort | Gabriele Ciarpi |
collection | DOAJ |
description | Links able to sustain high-speed data transfer while exposed to radiation phenomena are required by several applications, including aerospace and high-energy physics experiments. To satisfy this need, this paper outlines the design of a radiation-hard line driver for communication up to 10 Gb/s. The driver design is focused on the techniques adopted to increase its radiation hardness, namely the use of long-channel transistors, the avoidance of p-type MOSFETs and thick oxide devices. Circuital strategies to boost driver speed, such as inductive peaking, buffer chaining, and optimal layout placement and routing, are discussed and implemented to compensate for the downsides caused by adopted radiation-hard techniques. The driver, fabricated in 65 nm technology, has been experimentally tested demonstrating its ability to operate up to 10 Gb/s in a radiation-pervaded environment. In particular, after exposure to 1 Grad(SiO2) X-ray, the line driver exhibits an output signal amplitude reduction of 18.3% and a jitter increase of 5.53%. Performed temperature tests highlight that the line driver is capable to operate at 125 °C with 15.9% and 6.7% output signal swing reduction and jitter increase, respectively. The temperature tests also demonstrate the driver’s ability to work up to 160 °C with an output signal swing reduction below 25% and a jitter increase below 12%. |
first_indexed | 2024-03-12T20:53:40Z |
format | Article |
id | doaj.art-f4669416d4954635a541108a5f69af4e |
institution | Directory Open Access Journal |
issn | 2169-3536 |
language | English |
last_indexed | 2024-03-12T20:53:40Z |
publishDate | 2023-01-01 |
publisher | IEEE |
record_format | Article |
series | IEEE Access |
spelling | doaj.art-f4669416d4954635a541108a5f69af4e2023-07-31T23:00:48ZengIEEEIEEE Access2169-35362023-01-0111769417695210.1109/ACCESS.2023.329751510188687A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature ApplicationsGabriele Ciarpi0https://orcid.org/0000-0002-6056-2553Marco Mestice1https://orcid.org/0000-0003-2975-3471Daniele Rossi2https://orcid.org/0000-0002-9487-378XFabrizio Palla3https://orcid.org/0000-0002-6361-438XSergio Saponara4https://orcid.org/0000-0001-6724-4219Department of Information Engineering, University of Pisa, Pisa, ItalyDepartment of Information Engineering, University of Pisa, Pisa, ItalyDepartment of Information Engineering, University of Pisa, Pisa, ItalyNational Institute of Nuclear Physics, Pisa Section, Pisa, ItalyDepartment of Information Engineering, University of Pisa, Pisa, ItalyLinks able to sustain high-speed data transfer while exposed to radiation phenomena are required by several applications, including aerospace and high-energy physics experiments. To satisfy this need, this paper outlines the design of a radiation-hard line driver for communication up to 10 Gb/s. The driver design is focused on the techniques adopted to increase its radiation hardness, namely the use of long-channel transistors, the avoidance of p-type MOSFETs and thick oxide devices. Circuital strategies to boost driver speed, such as inductive peaking, buffer chaining, and optimal layout placement and routing, are discussed and implemented to compensate for the downsides caused by adopted radiation-hard techniques. The driver, fabricated in 65 nm technology, has been experimentally tested demonstrating its ability to operate up to 10 Gb/s in a radiation-pervaded environment. In particular, after exposure to 1 Grad(SiO2) X-ray, the line driver exhibits an output signal amplitude reduction of 18.3% and a jitter increase of 5.53%. Performed temperature tests highlight that the line driver is capable to operate at 125 °C with 15.9% and 6.7% output signal swing reduction and jitter increase, respectively. The temperature tests also demonstrate the driver’s ability to work up to 160 °C with an output signal swing reduction below 25% and a jitter increase below 12%.https://ieeexplore.ieee.org/document/10188687/Aerospacehigh energy physicshigh speedhigh temperatureintegrated circuitline driver |
spellingShingle | Gabriele Ciarpi Marco Mestice Daniele Rossi Fabrizio Palla Sergio Saponara A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications IEEE Access Aerospace high energy physics high speed high temperature integrated circuit line driver |
title | A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications |
title_full | A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications |
title_fullStr | A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications |
title_full_unstemmed | A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications |
title_short | A 10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation-Pervaded and High-Temperature Applications |
title_sort | 10 gb s line driver in 65 nm cmos technology for radiation pervaded and high temperature applications |
topic | Aerospace high energy physics high speed high temperature integrated circuit line driver |
url | https://ieeexplore.ieee.org/document/10188687/ |
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