Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA
This article presents a throughput/area accelerator for elliptic-curve point multiplication over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</...
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| Format: | Article |
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MDPI AG
2023-01-01
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| Series: | Applied Sciences |
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| Online Access: | https://www.mdpi.com/2076-3417/13/2/869 |
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| author | Ahmed Alhomoud Sajjad Shaukat Jamal Saleh M. Altowaijri Mohamed Ayari Adel R. Alharbi Amer Aljaedi |
| author_facet | Ahmed Alhomoud Sajjad Shaukat Jamal Saleh M. Altowaijri Mohamed Ayari Adel R. Alharbi Amer Aljaedi |
| author_sort | Ahmed Alhomoud |
| collection | DOAJ |
| description | This article presents a throughput/area accelerator for elliptic-curve point multiplication over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>571</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>. To optimize the throughput, we proposed an efficient hardware accelerator architecture for a fully recursive Karatsuba multiplier to perform polynomial multiplications in one clock cycle. To minimize the hardware resources, we have utilized the proposed Karatsuba multiplier for modular square implementations. Moreover, the Itoh-Tsujii algorithm for modular inverse computation is operated using multiplier resources. These strategies permit us to reduce the hardware resources of our implemented accelerator over a large field size of 571 bits. A controller is implemented to provide control functionalities. Our throughput/area accelerator is implemented in Verilog HDL using the Vivado IDE tool. The results after the place-and-route are given on Xilinx Virtex-6 and Virtex-7 devices. The utilized slices on Virtex-6 and Virtex-7 devices are 6107 and 5683, respectively. For the same FPGA devices, our accelerator can operate at a maximum of 319 MHz and 361 MHz. The latency values for Virtex-6 and Virtex-7 devices are 28.73 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s and 25.38 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s. The comparison to the state-of-the-art shows that the proposed architecture outperforms in throughput/area values. Thus, our accelerator architecture is suitable for cryptographic applications that demand a throughput and area simultaneously. |
| first_indexed | 2024-03-09T13:44:46Z |
| format | Article |
| id | doaj.art-f50012bcd3044e8abbcc87b24a94431f |
| institution | Directory Open Access Journal |
| issn | 2076-3417 |
| language | English |
| last_indexed | 2024-03-09T13:44:46Z |
| publishDate | 2023-01-01 |
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| record_format | Article |
| series | Applied Sciences |
| spelling | doaj.art-f50012bcd3044e8abbcc87b24a94431f2023-11-30T21:02:40ZengMDPI AGApplied Sciences2076-34172023-01-0113286910.3390/app13020869Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGAAhmed Alhomoud0Sajjad Shaukat Jamal1Saleh M. Altowaijri2Mohamed Ayari3Adel R. Alharbi4Amer Aljaedi5Department of Computer Sciences, Faculty of Computing and Information Technology, Northeren Border University, Rafha 91911, Saudi ArabiaDepartment of Mathematics, College of Science, King Khalid University, Abha 61413, Saudi ArabiaDepartment of Information Systems, Faculty of Computing and Information Technology, Northern Border University, Rafha 91911, Saudi ArabiaDepartment of Information Technology, Faculty of Computing and Information Technology, Northern Border University, Rafha 91911, Saudi ArabiaCollege of Computing and Information Technology, University of Tabuk, Tabuk 71491, Saudi ArabiaCollege of Computing and Information Technology, University of Tabuk, Tabuk 71491, Saudi ArabiaThis article presents a throughput/area accelerator for elliptic-curve point multiplication over <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mi>G</mi><mi>F</mi><mo>(</mo><msup><mn>2</mn><mn>571</mn></msup><mo>)</mo></mrow></semantics></math></inline-formula>. To optimize the throughput, we proposed an efficient hardware accelerator architecture for a fully recursive Karatsuba multiplier to perform polynomial multiplications in one clock cycle. To minimize the hardware resources, we have utilized the proposed Karatsuba multiplier for modular square implementations. Moreover, the Itoh-Tsujii algorithm for modular inverse computation is operated using multiplier resources. These strategies permit us to reduce the hardware resources of our implemented accelerator over a large field size of 571 bits. A controller is implemented to provide control functionalities. Our throughput/area accelerator is implemented in Verilog HDL using the Vivado IDE tool. The results after the place-and-route are given on Xilinx Virtex-6 and Virtex-7 devices. The utilized slices on Virtex-6 and Virtex-7 devices are 6107 and 5683, respectively. For the same FPGA devices, our accelerator can operate at a maximum of 319 MHz and 361 MHz. The latency values for Virtex-6 and Virtex-7 devices are 28.73 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s and 25.38 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>s. The comparison to the state-of-the-art shows that the proposed architecture outperforms in throughput/area values. Thus, our accelerator architecture is suitable for cryptographic applications that demand a throughput and area simultaneously.https://www.mdpi.com/2076-3417/13/2/869throughput/areahardware acceleratorelliptic-curvepoint multiplicationFPGA |
| spellingShingle | Ahmed Alhomoud Sajjad Shaukat Jamal Saleh M. Altowaijri Mohamed Ayari Adel R. Alharbi Amer Aljaedi Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA Applied Sciences throughput/area hardware accelerator elliptic-curve point multiplication FPGA |
| title | Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA |
| title_full | Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA |
| title_fullStr | Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA |
| title_full_unstemmed | Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA |
| title_short | Large Field-Size Throughput/Area Accelerator for Elliptic-Curve Point Multiplication on FPGA |
| title_sort | large field size throughput area accelerator for elliptic curve point multiplication on fpga |
| topic | throughput/area hardware accelerator elliptic-curve point multiplication FPGA |
| url | https://www.mdpi.com/2076-3417/13/2/869 |
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