Measurement of Power Dissipation Due to Parasitic Capacitances of Power MOSFETs

Measurement of Power Dissipation Due to Parasitic Capacitances of Power MOSFETs

Analysis of the switching losses in a power MOSFET is crucial for the design of efficient power electronic systems. Currently, the state-of-the-art technique is based on measured drain current and drain-to-source voltage during the switching intervals. However, this technique does not separate the s...

Deskribapen osoa

Xehetasun bibliografikoak
Egile Nagusiak: Utkarsh Jadli, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Jordan R. Nicholls, Sima Dimitrijev
Formatua: Artikulua
Hizkuntza:English
Argitaratua: IEEE 2020-01-01
Saila:IEEE Access
Gaiak:
Channel current
current diversion phenomenon
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efficiency
power losses
power MOSFET
Sarrera elektronikoa:https://ieeexplore.ieee.org/document/9220878/

Internet

https://ieeexplore.ieee.org/document/9220878/

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