Measurement of Power Dissipation Due to Parasitic Capacitances of Power MOSFETs
Analysis of the switching losses in a power MOSFET is crucial for the design of efficient power electronic systems. Currently, the state-of-the-art technique is based on measured drain current and drain-to-source voltage during the switching intervals. However, this technique does not separate the s...
| मुख्य लेखकों: | , , , , , |
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| स्वरूप: | लेख |
| भाषा: | English |
| प्रकाशित: |
IEEE
2020-01-01
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| श्रृंखला: | IEEE Access |
| विषय: | |
| ऑनलाइन पहुंच: | https://ieeexplore.ieee.org/document/9220878/ |