A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference
A dual-output CMOS voltage reference is presented for ultra-low power applications that require two or more different voltage references. The VREF1 is designed by employing the V<sub>TH</sub> difference between two devices to compensate the temperature coefficient (TC) of the thermal vol...
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/9127522/ |
| _version_ | 1818618892446072832 |
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| author | Jie Lin Lidan Wang Yan Lu Chenchang Zhan |
| author_facet | Jie Lin Lidan Wang Yan Lu Chenchang Zhan |
| author_sort | Jie Lin |
| collection | DOAJ |
| description | A dual-output CMOS voltage reference is presented for ultra-low power applications that require two or more different voltage references. The VREF1 is designed by employing the V<sub>TH</sub> difference between two devices to compensate the temperature coefficient (TC) of the thermal voltage. The V<sub>REF2</sub> is generated by feeding a current mirrored from the first reference voltage's supply current into a diode-connected-transistor load. In such a way, two different voltage references can be generated in one compact and simple design to reduce the devices and chip area significantly, compared to two separate voltage references in a conventional design. Fabricated in a 0.18-μm CMOS process, the proposed CMOS voltage reference can provide two references of 331.8 and 660.3 mV with variation coefficients of 0.53% and 0.42%, respectively. The average TCs of V<sub>REF1</sub> and V<sub>REF2</sub> for a temperature range of -40 to 125°C are measured as 41.7 and 24.5 ppm/°C, respectively. The line sensitivity (LS) of V<sub>REF1</sub> is 0.0505 %/V with 0.6-1.8 V supply, and the LS of V<sub>REF2</sub> is 0.114 %/V with 0.8-1.8 V supply. The measured results show a competitive power supply ripple rejection, and the power consumption is only 4.12 nW with 0.8-V minimum supply at 25°C, while the active area is 0.0108 mm<sup>2</sup>. |
| first_indexed | 2024-12-16T17:28:49Z |
| format | Article |
| id | doaj.art-f5a9f7ad9de54b4e888a2c000a531a3a |
| institution | Directory Open Access Journal |
| issn | 2644-1225 |
| language | English |
| last_indexed | 2024-12-16T17:28:49Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj.art-f5a9f7ad9de54b4e888a2c000a531a3a2022-12-21T22:22:59ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252020-01-01110010610.1109/OJCAS.2020.30055469127522A Nano-Watt Dual-Output Subthreshold CMOS Voltage ReferenceJie Lin0https://orcid.org/0000-0002-1777-6898Lidan Wang1https://orcid.org/0000-0002-3660-1524Yan Lu2https://orcid.org/0000-0001-9273-7576Chenchang Zhan3https://orcid.org/0000-0002-4878-4655State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaState Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, University of Macau, Macau, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaA dual-output CMOS voltage reference is presented for ultra-low power applications that require two or more different voltage references. The VREF1 is designed by employing the V<sub>TH</sub> difference between two devices to compensate the temperature coefficient (TC) of the thermal voltage. The V<sub>REF2</sub> is generated by feeding a current mirrored from the first reference voltage's supply current into a diode-connected-transistor load. In such a way, two different voltage references can be generated in one compact and simple design to reduce the devices and chip area significantly, compared to two separate voltage references in a conventional design. Fabricated in a 0.18-μm CMOS process, the proposed CMOS voltage reference can provide two references of 331.8 and 660.3 mV with variation coefficients of 0.53% and 0.42%, respectively. The average TCs of V<sub>REF1</sub> and V<sub>REF2</sub> for a temperature range of -40 to 125°C are measured as 41.7 and 24.5 ppm/°C, respectively. The line sensitivity (LS) of V<sub>REF1</sub> is 0.0505 %/V with 0.6-1.8 V supply, and the LS of V<sub>REF2</sub> is 0.114 %/V with 0.8-1.8 V supply. The measured results show a competitive power supply ripple rejection, and the power consumption is only 4.12 nW with 0.8-V minimum supply at 25°C, while the active area is 0.0108 mm<sup>2</sup>.https://ieeexplore.ieee.org/document/9127522/Dual-outputCMOS voltage referencesubthresholdultra-low power |
| spellingShingle | Jie Lin Lidan Wang Yan Lu Chenchang Zhan A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference IEEE Open Journal of Circuits and Systems Dual-output CMOS voltage reference subthreshold ultra-low power |
| title | A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference |
| title_full | A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference |
| title_fullStr | A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference |
| title_full_unstemmed | A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference |
| title_short | A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference |
| title_sort | nano watt dual output subthreshold cmos voltage reference |
| topic | Dual-output CMOS voltage reference subthreshold ultra-low power |
| url | https://ieeexplore.ieee.org/document/9127522/ |
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