Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques
This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (<inline-formula> <tex-math notation="LaTeX">$G_{\mathrm {max}}$...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10092735/ |
| _version_ | 1797847398017400832 |
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| author | Byeong-Taek Moon Byeonghun Yun Jusung Kim Sang-Gug Lee |
| author_facet | Byeong-Taek Moon Byeonghun Yun Jusung Kim Sang-Gug Lee |
| author_sort | Byeong-Taek Moon |
| collection | DOAJ |
| description | This article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (<inline-formula> <tex-math notation="LaTeX">$G_{\mathrm {max}}$ </tex-math></inline-formula>) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor’s nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the <inline-formula> <tex-math notation="LaTeX">$G_{\mathrm {max}}$ </tex-math></inline-formula> at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237–263 GHz), respectively, while requiring a chip area of 0.071 mm2. Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power. |
| first_indexed | 2024-04-09T18:10:43Z |
| format | Article |
| id | doaj.art-f5c086475f0d463cacd6c99a42542099 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-09T18:10:43Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-f5c086475f0d463cacd6c99a425420992023-04-13T23:00:35ZengIEEEIEEE Access2169-35362023-01-0111349423495110.1109/ACCESS.2023.326453110092735Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing TechniquesByeong-Taek Moon0https://orcid.org/0000-0002-4462-9594Byeonghun Yun1https://orcid.org/0000-0001-7847-1329Jusung Kim2https://orcid.org/0000-0002-3501-5910Sang-Gug Lee3https://orcid.org/0000-0001-8074-4090Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South KoreaDepartment of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South KoreaDepartment of Electronics Engineering, Hanbat National University, Daejeon, South KoreaDepartment of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South KoreaThis article presents a power-efficient frequency doubler employing gain boosting and harmonic-enhancing techniques. With a single transistor only, the gain boosting technique can reach the maximum achievable gain (<inline-formula> <tex-math notation="LaTeX">$G_{\mathrm {max}}$ </tex-math></inline-formula>) by adding embedded passive components, thereby obtaining high voltage swings. Then, the transistor’s nonlinearity is essential, which is maximized by the harmonic transition scheme of the transistor operation along with high voltage swings. In addition, a harmonic reflector and a harmonic leakage canceller are employed for the second harmonic enhancement. The harmonic reflector prevents unwanted harmonic mixing by minimizing the incoming second harmonic current fed back to the input. The harmonic leakage canceller suppresses the leakage loss of the second harmonic current present at the output. Furthermore, thanks to a proposed dual-band output matching network, the output impedance is conjugately matched to achieve the <inline-formula> <tex-math notation="LaTeX">$G_{\mathrm {max}}$ </tex-math></inline-formula> at the fundamental frequency while it is matched to extract the second harmonic output power simultaneously. To verify the proposed techniques, the prototype was designed as a single-stage circuit that does not require additional amplifying stages, which led to higher power efficiency and lower chip area. Implemented in a 65-nm CMOS process, the measurement results show a saturated output power of 0.9 dBm and 3-dB bandwidth of 26 GHz (237–263 GHz), respectively, while requiring a chip area of 0.071 mm2. Total power efficiency, including the effect of injected signal power, is 2.87 % while consuming only 37 mW dc power.https://ieeexplore.ieee.org/document/10092735/CMOSdual-band matching networkfrequency multiplierharmonic reflectormaximum achievable gainnonlinearity |
| spellingShingle | Byeong-Taek Moon Byeonghun Yun Jusung Kim Sang-Gug Lee Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques IEEE Access CMOS dual-band matching network frequency multiplier harmonic reflector maximum achievable gain nonlinearity |
| title | Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques |
| title_full | Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques |
| title_fullStr | Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques |
| title_full_unstemmed | Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques |
| title_short | Analysis and Design of Power-Efficient H-Band CMOS Frequency Doubler Employing Gain Boosting and Harmonic Enhancing Techniques |
| title_sort | analysis and design of power efficient h band cmos frequency doubler employing gain boosting and harmonic enhancing techniques |
| topic | CMOS dual-band matching network frequency multiplier harmonic reflector maximum achievable gain nonlinearity |
| url | https://ieeexplore.ieee.org/document/10092735/ |
| work_keys_str_mv | AT byeongtaekmoon analysisanddesignofpowerefficienthbandcmosfrequencydoubleremployinggainboostingandharmonicenhancingtechniques AT byeonghunyun analysisanddesignofpowerefficienthbandcmosfrequencydoubleremployinggainboostingandharmonicenhancingtechniques AT jusungkim analysisanddesignofpowerefficienthbandcmosfrequencydoubleremployinggainboostingandharmonicenhancingtechniques AT sangguglee analysisanddesignofpowerefficienthbandcmosfrequencydoubleremployinggainboostingandharmonicenhancingtechniques |