Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application
High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encrypti...
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Format: | Article |
Language: | English |
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IEEE
2020-01-01
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Series: | IEEE Access |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/9025068/ |
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author | Syed Jahanzeb Hussain Pirzada Abid Murtaza Tongge Xu Liu Jianwei |
author_facet | Syed Jahanzeb Hussain Pirzada Abid Murtaza Tongge Xu Liu Jianwei |
author_sort | Syed Jahanzeb Hussain Pirzada |
collection | DOAJ |
description | High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it's compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations. |
first_indexed | 2024-12-17T00:45:45Z |
format | Article |
id | doaj.art-f6331aaabed34e03b711c425be083645 |
institution | Directory Open Access Journal |
issn | 2169-3536 |
language | English |
last_indexed | 2024-12-17T00:45:45Z |
publishDate | 2020-01-01 |
publisher | IEEE |
record_format | Article |
series | IEEE Access |
spelling | doaj.art-f6331aaabed34e03b711c425be0836452022-12-21T22:09:55ZengIEEEIEEE Access2169-35362020-01-018485434855610.1109/ACCESS.2020.29786659025068Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite ApplicationSyed Jahanzeb Hussain Pirzada0https://orcid.org/0000-0002-9202-5859Abid Murtaza1https://orcid.org/0000-0002-8065-0518Tongge Xu2https://orcid.org/0000-0002-0135-7226Liu Jianwei3https://orcid.org/0000-0003-2965-3518School of Cyber Science and Technology, Beihang University, Beijing, ChinaSchool of Cyber Science and Technology, Beihang University, Beijing, ChinaSchool of Cyber Science and Technology, Beihang University, Beijing, ChinaSchool of Cyber Science and Technology, Beihang University, Beijing, ChinaHigh-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it's compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.https://ieeexplore.ieee.org/document/9025068/Authenticated encryptionFPGAnonce misuse attackparallel architecturesatellite communicationside-channel attack |
spellingShingle | Syed Jahanzeb Hussain Pirzada Abid Murtaza Tongge Xu Liu Jianwei Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application IEEE Access Authenticated encryption FPGA nonce misuse attack parallel architecture satellite communication side-channel attack |
title | Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application |
title_full | Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application |
title_fullStr | Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application |
title_full_unstemmed | Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application |
title_short | Architectural Optimization of Parallel Authenticated Encryption Algorithm for Satellite Application |
title_sort | architectural optimization of parallel authenticated encryption algorithm for satellite application |
topic | Authenticated encryption FPGA nonce misuse attack parallel architecture satellite communication side-channel attack |
url | https://ieeexplore.ieee.org/document/9025068/ |
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