A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection

A RISC-V Fault-Tolerant Soft-Processor Based on Full/Partial Heterogeneous Dual-Core Protection

The low probability of single event upsets (SEU) within particular satellite orbits, makes Commercial-off-the-shelf (COTS) electronic components a viable solution for space system implementation, thanks to the introduction of design-level fault tolerance techniques at the expense of some performance...

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Bibliographic Details
Main Authors: Francesco Vigli, Marcello Barbirotta, Abdallah Cheikh, Francesco Menichelli, Antonio Mastrandrea, Mauro Olivieri
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Processor architecture
fault-tolerance
multi-core
RISC-V
interleaved multi-threading
heterogeneous computing
Online Access:https://ieeexplore.ieee.org/document/10438461/

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https://ieeexplore.ieee.org/document/10438461/

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