Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks

Side channel analysis and fault attacks are two powerful methods to analyze and break cryptographic implementations. At CHES 2011, Roche and Prouff applied secure multiparty computation to prevent side-channel attacks. While multiparty computation is known to be fault-resistant as well, the particul...

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Main Authors: Okan Seker, Abraham Fernandez-Rubio, Thomas Eisenbarth, Rainer Steinwandt
Format: Article
Language:English
Published: Ruhr-Universität Bochum 2018-08-01
Series:Transactions on Cryptographic Hardware and Embedded Systems
Subjects:
Online Access:https://tches.iacr.org/index.php/TCHES/article/view/7281
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author Okan Seker
Abraham Fernandez-Rubio
Thomas Eisenbarth
Rainer Steinwandt
author_facet Okan Seker
Abraham Fernandez-Rubio
Thomas Eisenbarth
Rainer Steinwandt
author_sort Okan Seker
collection DOAJ
description Side channel analysis and fault attacks are two powerful methods to analyze and break cryptographic implementations. At CHES 2011, Roche and Prouff applied secure multiparty computation to prevent side-channel attacks. While multiparty computation is known to be fault-resistant as well, the particular scheme used for side-channel protection does not currently offer this feature. This work introduces a new secure multiparty circuit to prevent both fault injection attacks and sidechannel analysis. The new scheme extends the Roche and Prouff scheme to make faults detectable. Arithmetic operations have been redesigned to propagate fault information until a new secrecy-preserving fault detection can be performed. A new recombination operation ensures randomization of the output in the case of a fault, ensuring that nothing can be learned from the faulty output. The security of the new scheme is proved in the ISW probing model, using the reformulated t-SNI security notion. Besides the new scheme and its security proof, we also present an extensive performance analysis, including a proof-of-concept, software-based AES implementation featuring the masking technique to resist both fault and side-channel attacks at the same time. The performance analysis for different security levels are given for the ARM-M0+ MCU with its memory requirements. A comprehensive leakage analysis shows that a careful implementation of the scheme achieves the expected security level.
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spelling doaj.art-f84c24aabdd34f838802b5a636e777822022-12-22T01:36:27ZengRuhr-Universität BochumTransactions on Cryptographic Hardware and Embedded Systems2569-29252018-08-012018310.13154/tches.v2018.i3.394-430Extending Glitch-Free Multiparty Protocols to Resist Fault Injection AttacksOkan Seker0Abraham Fernandez-Rubio1Thomas Eisenbarth2Rainer Steinwandt3University of LübeckIntelUniversity of Lübeck, Germany; Worcester Polytechnic InstituteFlorida Atlantic UniversitySide channel analysis and fault attacks are two powerful methods to analyze and break cryptographic implementations. At CHES 2011, Roche and Prouff applied secure multiparty computation to prevent side-channel attacks. While multiparty computation is known to be fault-resistant as well, the particular scheme used for side-channel protection does not currently offer this feature. This work introduces a new secure multiparty circuit to prevent both fault injection attacks and sidechannel analysis. The new scheme extends the Roche and Prouff scheme to make faults detectable. Arithmetic operations have been redesigned to propagate fault information until a new secrecy-preserving fault detection can be performed. A new recombination operation ensures randomization of the output in the case of a fault, ensuring that nothing can be learned from the faulty output. The security of the new scheme is proved in the ISW probing model, using the reformulated t-SNI security notion. Besides the new scheme and its security proof, we also present an extensive performance analysis, including a proof-of-concept, software-based AES implementation featuring the masking technique to resist both fault and side-channel attacks at the same time. The performance analysis for different security levels are given for the ARM-M0+ MCU with its memory requirements. A comprehensive leakage analysis shows that a careful implementation of the scheme achieves the expected security level.https://tches.iacr.org/index.php/TCHES/article/view/7281Secure multiparty computationSide-channel analysisFault attacksPolynomial MaskingARM
spellingShingle Okan Seker
Abraham Fernandez-Rubio
Thomas Eisenbarth
Rainer Steinwandt
Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks
Transactions on Cryptographic Hardware and Embedded Systems
Secure multiparty computation
Side-channel analysis
Fault attacks
Polynomial Masking
ARM
title Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks
title_full Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks
title_fullStr Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks
title_full_unstemmed Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks
title_short Extending Glitch-Free Multiparty Protocols to Resist Fault Injection Attacks
title_sort extending glitch free multiparty protocols to resist fault injection attacks
topic Secure multiparty computation
Side-channel analysis
Fault attacks
Polynomial Masking
ARM
url https://tches.iacr.org/index.php/TCHES/article/view/7281
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AT abrahamfernandezrubio extendingglitchfreemultipartyprotocolstoresistfaultinjectionattacks
AT thomaseisenbarth extendingglitchfreemultipartyprotocolstoresistfaultinjectionattacks
AT rainersteinwandt extendingglitchfreemultipartyprotocolstoresistfaultinjectionattacks