Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology
Abstract A method is presented for the design of high‐speed frequency dividers in which the divided output signals are phase aligned by means of a scheme based on cascaded retiming. The objective of the design method proposed is to break the accumulation of propagation delay occurring in a divider c...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-12-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/ell2.13033 |