Novel level and edge-triggered universal shift registers with low latency in QCA technology
Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performan...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Elsevier
2024-03-01
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| Series: | Heliyon |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2405844024021170 |
| _version_ | 1797259974432260096 |
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| author | Mojtaba Gholamnia Roshan Mohammad Gholami |
| author_facet | Mojtaba Gholamnia Roshan Mohammad Gholami |
| author_sort | Mojtaba Gholamnia Roshan |
| collection | DOAJ |
| description | Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clocks. |
| first_indexed | 2024-03-07T18:36:45Z |
| format | Article |
| id | doaj.art-f92ae1de64ea4280bb1aebf24d04664a |
| institution | Directory Open Access Journal |
| issn | 2405-8440 |
| language | English |
| last_indexed | 2024-04-24T23:17:57Z |
| publishDate | 2024-03-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Heliyon |
| spelling | doaj.art-f92ae1de64ea4280bb1aebf24d04664a2024-03-17T07:55:10ZengElsevierHeliyon2405-84402024-03-01105e26086Novel level and edge-triggered universal shift registers with low latency in QCA technologyMojtaba Gholamnia Roshan0Mohammad Gholami1Department of Electrical Engineering, Mazandaran Institute of Technology, Babol, IranUniversity of Mazandaran, Babolsar, Iran; Corresponding author.Shift registers are one of the main blocks in processors. In this paper, two new universal shift registers are designed based on Quantum-Dot Cellular Automata (QCA) nanotechnology. Both of the proposed level triggered and edge triggered universal shift register in QCA technology shows good performance in regards of the number of cells, occupied area, delay, and power. These designs also have reset abilities. Simulations show that the proposed 4-bit level triggered universal shift register with reset ability has 1057 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clock. In addition, the proposed rising edge triggered 4-bit universal shift register with reset ability has 1085 QCA cells, 1.27 μm2 occupied area, and delay of about three cycles of QCA clocks.http://www.sciencedirect.com/science/article/pii/S2405844024021170QCAShift registerLatencyLatch |
| spellingShingle | Mojtaba Gholamnia Roshan Mohammad Gholami Novel level and edge-triggered universal shift registers with low latency in QCA technology Heliyon QCA Shift register Latency Latch |
| title | Novel level and edge-triggered universal shift registers with low latency in QCA technology |
| title_full | Novel level and edge-triggered universal shift registers with low latency in QCA technology |
| title_fullStr | Novel level and edge-triggered universal shift registers with low latency in QCA technology |
| title_full_unstemmed | Novel level and edge-triggered universal shift registers with low latency in QCA technology |
| title_short | Novel level and edge-triggered universal shift registers with low latency in QCA technology |
| title_sort | novel level and edge triggered universal shift registers with low latency in qca technology |
| topic | QCA Shift register Latency Latch |
| url | http://www.sciencedirect.com/science/article/pii/S2405844024021170 |
| work_keys_str_mv | AT mojtabagholamniaroshan novellevelandedgetriggereduniversalshiftregisterswithlowlatencyinqcatechnology AT mohammadgholami novellevelandedgetriggereduniversalshiftregisterswithlowlatencyinqcatechnology |