Implementation of RSA Signatures on GPU and CPU Architectures
This paper reports a constant-time CPU and GPU software implementation of the RSA exponentiation by using algorithms that offer a first-line defense against timing and cache attacks. In the case of GPU platforms the modular arithmetic layer was implemented using the Residue Number System (RNS) repre...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8949525/ |
| _version_ | 1819276653436600320 |
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| author | Eduardo Ochoa-Jimenez Luis Rivera-Zamarripa Nareli Cruz-Cortes Francisco Rodriguez-Henriquez |
| author_facet | Eduardo Ochoa-Jimenez Luis Rivera-Zamarripa Nareli Cruz-Cortes Francisco Rodriguez-Henriquez |
| author_sort | Eduardo Ochoa-Jimenez |
| collection | DOAJ |
| description | This paper reports a constant-time CPU and GPU software implementation of the RSA exponentiation by using algorithms that offer a first-line defense against timing and cache attacks. In the case of GPU platforms the modular arithmetic layer was implemented using the Residue Number System (RNS) representation. We also present a CPU implementation of an RNS-based arithmetic that takes advantage of the parallelism provided by the Advanced Vector Extensions 2 (AVX2) instructions. Moreover, we carefully analyze the performance of two popular RNS modular reduction algorithms when implemented on many- and multi-core platforms. In the case of CPU platforms we also report that a combination of the schoolbook and Karatsuba algorithms for integer multiplication along with Montgomery reduction, yields our fastest modular multiplication procedure. In comparison with previous literature, our software library achieves faster timings for the computation of the RSA exponentiation using 1024-, 2048- and 3072-bit private keys. |
| first_indexed | 2024-12-23T23:43:38Z |
| format | Article |
| id | doaj.art-f9beffdc056b4618817e7369c903c641 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-23T23:43:38Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-f9beffdc056b4618817e7369c903c6412022-12-21T17:25:35ZengIEEEIEEE Access2169-35362020-01-0189928994110.1109/ACCESS.2019.29638268949525Implementation of RSA Signatures on GPU and CPU ArchitecturesEduardo Ochoa-Jimenez0https://orcid.org/0000-0002-7349-8546Luis Rivera-Zamarripa1https://orcid.org/0000-0002-1779-421XNareli Cruz-Cortes2https://orcid.org/0000-0003-4827-0184Francisco Rodriguez-Henriquez3https://orcid.org/0000-0002-5916-6625Computer Science Department, Cinvestav, Mexico City, MexicoCentro de Investigación en Computación, Instituto Politécnico Nacional, Mexico City, MexicoCentro de Investigación en Computación, Instituto Politécnico Nacional, Mexico City, MexicoComputer Science Department, Cinvestav, Mexico City, MexicoThis paper reports a constant-time CPU and GPU software implementation of the RSA exponentiation by using algorithms that offer a first-line defense against timing and cache attacks. In the case of GPU platforms the modular arithmetic layer was implemented using the Residue Number System (RNS) representation. We also present a CPU implementation of an RNS-based arithmetic that takes advantage of the parallelism provided by the Advanced Vector Extensions 2 (AVX2) instructions. Moreover, we carefully analyze the performance of two popular RNS modular reduction algorithms when implemented on many- and multi-core platforms. In the case of CPU platforms we also report that a combination of the schoolbook and Karatsuba algorithms for integer multiplication along with Montgomery reduction, yields our fastest modular multiplication procedure. In comparison with previous literature, our software library achieves faster timings for the computation of the RSA exponentiation using 1024-, 2048- and 3072-bit private keys.https://ieeexplore.ieee.org/document/8949525/Public key cryptographyRSARNS arithmeticGPUCPUAVX2 instructions |
| spellingShingle | Eduardo Ochoa-Jimenez Luis Rivera-Zamarripa Nareli Cruz-Cortes Francisco Rodriguez-Henriquez Implementation of RSA Signatures on GPU and CPU Architectures IEEE Access Public key cryptography RSA RNS arithmetic GPU CPU AVX2 instructions |
| title | Implementation of RSA Signatures on GPU and CPU Architectures |
| title_full | Implementation of RSA Signatures on GPU and CPU Architectures |
| title_fullStr | Implementation of RSA Signatures on GPU and CPU Architectures |
| title_full_unstemmed | Implementation of RSA Signatures on GPU and CPU Architectures |
| title_short | Implementation of RSA Signatures on GPU and CPU Architectures |
| title_sort | implementation of rsa signatures on gpu and cpu architectures |
| topic | Public key cryptography RSA RNS arithmetic GPU CPU AVX2 instructions |
| url | https://ieeexplore.ieee.org/document/8949525/ |
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