| 總結: | This article reports a 110.2 MHz ultra-low-power phase-locked loop (PLL) for MEMS timing/frequency reference oscillator applications. It utilizes a 6.89 MHz MEMS-based oscillator as an input reference. An ultra-low-power, high-resolution phase-frequency detector (PFD) is utilized to achieve low-noise performance. Eliminating the reset feedback path used in conventional PFDs leads to dead/blind zone-free phase characteristics, which are crucial for low-noise applications within a wide operating frequency range. The PFD operates up to 2.5 GHz and achieves a linear resolution of 100 ps input time difference (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>Δ</mo><msub><mi>t</mi><mrow><mi>i</mi><mi>n</mi></mrow></msub></mrow></semantics></math></inline-formula>), without the need for any additional calibration circuits. The linearity of the proposed PFD is tested over a phase difference corresponding to aa <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>Δ</mo><msub><mi>t</mi><mrow><mi>i</mi><mi>n</mi></mrow></msub></mrow></semantics></math></inline-formula> ranging from 100 ps to 50 ns. At a 1 V supply voltage, it shows an error of <±1.6% with a resolution of 100 ps and a frequency-normalized power consumption (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msub><mi>P</mi><mi>n</mi></msub></semantics></math></inline-formula>) of 0.106 pW/Hz. The PLL is designed and fabricated using a TSMC 65 nm CMOS process instrument and interfaced with the MEMS-based oscillator. The system reports phase noises of −106.21 dBc/Hz and −135.36 dBc/Hz at 1 kHz and 1 MHz offsets, respectively. It consumes 6.709 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W at a 1 V supply and occupies an active CMOS area of 0.1095 mm<sup>2</sup>.
|
|---|