A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture
This paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is to remove mandato...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-10-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/21/3438 |
| _version_ | 1797468544391184384 |
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| author | Ehsan Ali Wanchalerm Pora |
| author_facet | Ehsan Ali Wanchalerm Pora |
| author_sort | Ehsan Ali |
| collection | DOAJ |
| description | This paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is to remove mandatory branch and load delays to achieve a uniform one clock cycle per every instruction. To demonstrate the concept, the proposed architecture is applied to the Xilinx PicoBlaze firm core. The result is a new soft core named DAP-Zipi8 that reduces the clock per instruction (CPI) metric of PicoBlaze from two to one at the expense of extra logic and a longer critical path. The increased critical path reduces maximum achievable clock speed from 357.509 MHz to 224.022 MHz. Merging the gain in CPI with the loss in maximum clock frequency still improves overall processor performance by 18.28–19.49%. The high-performance deterministic DAP-Zipi8 is a viable choice for hard RTES applications. |
| first_indexed | 2024-03-09T19:08:56Z |
| format | Article |
| id | doaj.art-fa861c9e76cc41338eb94c6fa1d0b353 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T19:08:56Z |
| publishDate | 2022-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-fa861c9e76cc41338eb94c6fa1d0b3532023-11-24T04:23:58ZengMDPI AGElectronics2079-92922022-10-011121343810.3390/electronics11213438A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze ArchitectureEhsan Ali0Wanchalerm Pora1Department of Electrical Engineering, Faculty of Engineering, Chulalongkorn University, Bangkok 10330, ThailandDepartment of Electrical Engineering, Faculty of Engineering, Chulalongkorn University, Bangkok 10330, ThailandThis paper proposes a new deterministic branch prediction unit to achieve a uniformly timed instruction set architecture (ISA). The deterministic ISA is achieved by utilizing two address buses in conjunction with dual-port block RAMs that are common in commercial FPGAs. The goal is to remove mandatory branch and load delays to achieve a uniform one clock cycle per every instruction. To demonstrate the concept, the proposed architecture is applied to the Xilinx PicoBlaze firm core. The result is a new soft core named DAP-Zipi8 that reduces the clock per instruction (CPI) metric of PicoBlaze from two to one at the expense of extra logic and a longer critical path. The increased critical path reduces maximum achievable clock speed from 357.509 MHz to 224.022 MHz. Merging the gain in CPI with the loss in maximum clock frequency still improves overall processor performance by 18.28–19.49%. The high-performance deterministic DAP-Zipi8 is a viable choice for hard RTES applications.https://www.mdpi.com/2079-9292/11/21/3438FPGAfield programmable gate arraysmicroprocessorsreal-time embedded systemsXilinx PicoBlazedeterministic instruction set architecture |
| spellingShingle | Ehsan Ali Wanchalerm Pora A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture Electronics FPGA field programmable gate arrays microprocessors real-time embedded systems Xilinx PicoBlaze deterministic instruction set architecture |
| title | A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture |
| title_full | A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture |
| title_fullStr | A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture |
| title_full_unstemmed | A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture |
| title_short | A Deterministic Branch Prediction Technique for a Real-Time Embedded Processor Based on PicoBlaze Architecture |
| title_sort | deterministic branch prediction technique for a real time embedded processor based on picoblaze architecture |
| topic | FPGA field programmable gate arrays microprocessors real-time embedded systems Xilinx PicoBlaze deterministic instruction set architecture |
| url | https://www.mdpi.com/2079-9292/11/21/3438 |
| work_keys_str_mv | AT ehsanali adeterministicbranchpredictiontechniqueforarealtimeembeddedprocessorbasedonpicoblazearchitecture AT wanchalermpora adeterministicbranchpredictiontechniqueforarealtimeembeddedprocessorbasedonpicoblazearchitecture AT ehsanali deterministicbranchpredictiontechniqueforarealtimeembeddedprocessorbasedonpicoblazearchitecture AT wanchalermpora deterministicbranchpredictiontechniqueforarealtimeembeddedprocessorbasedonpicoblazearchitecture |