General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers
This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalabil...
| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-10-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/12/20/4211 |
| _version_ | 1797574101735309312 |
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| author | Vassilis Alimisis Nikolaos P. Eleftheriou Argyro Kamperi Georgios Gennis Christos Dimas Paul P. Sotiriadis |
| author_facet | Vassilis Alimisis Nikolaos P. Eleftheriou Argyro Kamperi Georgios Gennis Christos Dimas Paul P. Sotiriadis |
| author_sort | Vassilis Alimisis |
| collection | DOAJ |
| description | This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity. |
| first_indexed | 2024-03-10T21:18:10Z |
| format | Article |
| id | doaj.art-fa9f38edb909416285cccda4b5273ab6 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T21:18:10Z |
| publishDate | 2023-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-fa9f38edb909416285cccda4b5273ab62023-11-19T16:18:24ZengMDPI AGElectronics2079-92922023-10-011220421110.3390/electronics12204211General Methodology for the Design of Bell-Shaped Analog-Hardware ClassifiersVassilis Alimisis0Nikolaos P. Eleftheriou1Argyro Kamperi2Georgios Gennis3Christos Dimas4Paul P. Sotiriadis5Department of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, GreeceDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, GreeceDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, GreeceDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, GreeceDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, GreeceDepartment of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, GreeceThis study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.https://www.mdpi.com/2079-9292/12/20/4211analog VLSIgeneral design methodologybiomedical applicationswake-up circuitanalog classifiers |
| spellingShingle | Vassilis Alimisis Nikolaos P. Eleftheriou Argyro Kamperi Georgios Gennis Christos Dimas Paul P. Sotiriadis General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers Electronics analog VLSI general design methodology biomedical applications wake-up circuit analog classifiers |
| title | General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers |
| title_full | General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers |
| title_fullStr | General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers |
| title_full_unstemmed | General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers |
| title_short | General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers |
| title_sort | general methodology for the design of bell shaped analog hardware classifiers |
| topic | analog VLSI general design methodology biomedical applications wake-up circuit analog classifiers |
| url | https://www.mdpi.com/2079-9292/12/20/4211 |
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