| Summary: | In this paper we analyze, design and compare six significant topologies of one-bit full adders in terms of their Energy-Efficient Curves in the Energy-Delay Space. We define the simulation strategies that are adopted to make a fair comparison even among cells with very different characteristics. Each topology is designed through a methodology which, thanks to the adoption of a circuit optimizer, allows to design the circuit under different energy-delay trade-offs and to derive the Energy-Efficient Curves. The comparison of the topologies is made using a 28nm CMOS technology in terms of normalized Energy-Efficient Curves. In particular, plotting all these Energy-Efficient Curves in a single graph makes the comparison very effective and allows the designer to choose the best topology or discard the worst ones, at a glance.
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