Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet
In this paper, after calibrating the models and parameters used in the simulations based on experimental data, by using the opposite doping in the channel and between the gates in an asymmetric double-gate junctionless (JL) transistor with the 3nm gate length, a charge sheet (CS) was created. The re...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2022-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9755940/ |